CPU32 Instructions

7-4

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

MOTOROLA

BGND

Enter Background Mode

BGND

(CPU32)

Operation:

If Background Mode Enabled

Then Enter Background Mode

Else Format/Vector Offset

→

– (SSP);

→

– (SSP)

→

– (SSP)

(Vector)

→

Assembler

Syntax:

BGND

Attributes:

Size = (Unsized)

Description:

The processor suspends instruction execution and enters background mode

if background mode is enabled. The freeze output is asserted to acknowledge entrance

into background mode. Upon exiting background mode, instruction execution

continues with the instruction pointed to by the current program counter. If background

mode is not enabled, the processor initiates illegal instruction exception processing.

The vector number is generated to reference the illegal instruction exception vector.

Refer to the appropriate user’s manual for detailed information on background mode.

Condition Codes:

X — Not affected.

N — Not affected.

Z — Not affected.

V — Not affected.

C — Not affected.

Instruction Format:

XNZVC

—————

1514131211109876543210

0100101011111010

CPU32 Instructions

MOTOROLA

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

7-5

LPSTOP

Low-Power Stop

LPSTOP

(CPU32)

Operation:

If Supervisor State

Immediate Data

→

Interrupt Mask

→

External Bus Interface (EBI)

STOP

Else TRAP

Assembler

Syntax:

LPSTOP # < data >

Attributes:

Size = (Word) Privileged

Description:

The immediate operand moves into the entire status register, the program

counter advances to point to the next instruction, and the processor stops fetching and

executing instructions. A CPU LPSTOP broadcast cycle is executed to CPU space $3

to copy the updated interrupt mask to the external bus interface (EBI). The internal

clocks are stopped.

Instruction execution resumes when a trace, interrupt, or reset exception occurs. A

trace exception will occur if the trace state is on when the LPSTOP instruction is

executed. If an interrupt request is asserted with a higher priority that the current

priority level set by the new status register value, an interrupt exception occurs;

otherwise, the interrupt request is ignored. If the bit of the immediate data

corresponding to the S-bit is off, execution of the instruction will cause a privilege

violation. An external reset always initiates reset exception processing.

Condition Codes:

Set according to the immediate operand.

Instruction Format:

Instruction Fields:

Immediate ﬁeld—Speciﬁes the data to be loaded into the status register.

1514131211109876543210

1111100000000000

0000000111000000

IMMEDIATE DATA

CPU32 Instructions

7-6

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

MOTOROLA

TBLS TBLS

TBLSN

Table Lookup and Interpolate (Signed)

TBLSN

(CPU32)

Operation:

Rounded:

ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0}

256

→

Unrounded:

ENTRY(n) x 256 + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0}

→

Where ENTRY(n) and ENTRY(n + 1) are either:

1. Consecutive entries in the table pointed to by the < ea > and

indexed by Dx 15 – 8

SIZE or;

2. The registers Dym, Dyn respectively.

Assembler

TBLS. < size > < ea > ,Dx Result rounded

Syntax:

TBLSN. < size > < ea > ,Dx Result not rounded

TBLS. < size > Dym:Dyn, Dx Result rounded

TBLSN. < size > Dym:Dyn, Dx Result not rounded

Attributes:

Size = (Byte, Word, Long)

Description:

The TBLS and TBLSN instructions allow the efﬁcient use of piecewise linear

compressed data tables to model complex functions. The TBLS instruction has two

modes of operation: table lookup and interpolate mode and data register interpolate

mode.

For table lookup and interpolate mode, data register Dx 15 – 0 contains the

independent variable X. The effective address points to the start of a signed byte, word,

or long-word table containing a linearized representation of the dependent variable, Y,

as a function of X. In general, the independent variable, located in the low-order word

of Dx, consists of an 8-bit integer part and an 8-bit fractional part. An assumed radix

point is located between bits 7 and 8. The integer part, Dx 15 – 8, is scaled by the

operand size and is used as an offset into the table. The selected entry in the table is

subtracted from the next consecutive entry. A fractional portion of this difference is

taken by multiplying by the interpolation fraction, Dx 7 – 0 .The adjusted difference is

then added to the selected table entry. The result is returned in the destination data

CPU32 Instructions

MOTOROLA

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

7-7

TBLS TBLS

TBLSN

Table Lookup and Interpolate (Signed)

TBLSN

(CPU32)

For register interpolate mode, the interpolation occurs using the Dym and Dyn registers

in place of the two table entries. For this mode, only the fractional portion, Dx 7 – 0, is

used in the interpolation, and the integer portion, Dx 15 – 8, is ignored. The register

interpolation mode may be used with several table lookup and interpolations to model

multidimensional functions.

Signed table entries range from – 2

n – 1

to 2

n – 1

– 1; whereas, unsigned table entries

range from 0 to 2

n – 1

where n is 8, 16, or 32 for byte, word, and long-word tables,

respectively.

Rounding of the result is optionally selected via the "R" instruction field. If R = 0

(TABLE), the fractional portion is rounded according to the round-to-nearest algorithm.

The following table summerizes the rounding procedure:

The adjusted difference is then added to the selected table entry. The rounded result

is returned in the destination data register, Dx. Only the portion of the register

corresponding to the selected size is affected.

Adjusted Difference

Fraction Rounding

Adjustment

≤

– 1/2 – 1

> – 1/2 and < 1/2 + 0

≥

1/2 + 1

31 24 23 16 15 8 7 0

BYTE UNAFFECTED UNAFFECTED UNAFFECTED RESULT

WORD UNAFFECTED UNAFFECTED RESULT RESULT

LONG RESULT RESULT RESULT RESULT

CPU32 Instructions

7-8

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

MOTOROLA

TBLS TBLS

TBLSN

Table Lookup and Interpolate (Signed)

TBLSN

(CPU32)

If R = 1 (TABLENR), the result is returned in register Dx without rounding. If the size is

byte, the integer portion of the result is returned in Dx 15 – 8; the integer portion of a

word result is stored in Dx 23 – 8; the least significant 24 bits of a long result are stored

in Dx 31 – 8. Byte and word results are sign-extended to fill the entire 32-bit register.

NOTE

The long-word result contains only the least signiﬁcant 24 bits of

integer precision.

For all sizes, the 8-bit fractional portion of the result is returned to the low byte of the

data register, Dx 7 – 0. User software can make use of the fractional data to reduce

cumulative errors in lengthy calculations or implement rounding algorithms different

from that provided by other forms of TBLS. The previously described assumed radix

point places two restrictions on the programmer:

1. Tables are limited to 257 entries in length.

2. Interpolation resolution is limited to 1/256, the distance between consecutive ta-

ble entries. The assumed radix point should not, however, be construed by the

programmer as a requirement that the independent variable be calculated as a

fractional number in the range 0 <

< 255. On the contrary, X should be consid-

ered an integer in the range 0 <

< 65535, realizing that the table is actually a

compressed representation of a linearized function in which only every 256th

value is actually stored in memory.

31 24 23 16 15 8 7 0

BYTE SIGN-EXTENDED SIGN-EXTENDED RESULT FRACTION

WORD SIGN-EXTENDED RESULT RESULT FRACTION

LONG RESULT RESULT RESULT FRACTION

CPU32 Instructions

MOTOROLA

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

7-9

TBLS TBLS

TBLSN

Table Lookup and Interpolate (Signed)

TBLSN

(CPU32)

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the result is set; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if the integer portion of an unrounded long result is not in the range, – (2

)

≤

Result

≤

) – 1; cleared otherwise.

C — Always cleared.

Instruction Format:

TABLE LOOKUP AND INTERPOLATE

DATA REGISTER INTERPOLATE

XNZVC

—

∗∗∗

1514131211109876543210

1111100000 EFFECTIVE ADDRESS

MODE REGISTER

0 REGISTER Dx 1 R 0 1 SIZE 00000 0

1514131211109876543210

1111100000000 REGISTER Dym

0 REGISTER Dx 1 R 0 1 SIZE 0 0 0 REGISTER Dyn

CPU32 Instructions

7-10

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

TBLS TBLS

TBLSN Table Lookup and Interpolate (Signed) TBLSN

(CPU32)

Instruction Fields:

Effective address ﬁeld (table lookup and interpolate mode only)—Speciﬁes the

destination location. Only control alterable addressing modes are allowed as listed

in the following table:

Size Field—Speciﬁes the size of operation.

00 — Byte Operation

01 — Word Operation

10 — Long Operation

contains the interpolation fraction and entry number.

Dym, Dyn ﬁeld—If the effective address mode ﬁeld is nonzero, this operand register is

unused and should be zero. If the effective address mode ﬁeld is zero, the surface

interpolation variant of this instruction is implied, and Dyn speciﬁes one of the two

source operands.

Rounding mode ﬁeld—The R-bit controls the rounding of the ﬁnal result. When R = 0,

the result is rounded according to the round-to-nearest algorithm. When R = 1, the

result is returned unrounded.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) — — # < data > — —

(An) + — —

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

CPU32 Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 7-11

TBLU TBLU

TBLUN Table Lookup and Interpolation (Unsigned) TBLUN

(CPU32)

Operation: Rounded:

ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0} ÷ 256 → Dx

Unrounded:

ENTRY(n) x 256 + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0} → Dx

Where ENTRY(n) and ENTRY(n + 1) are either:

1. Consecutive entries in the table pointed to by the < ea > and

indexed by Dx 15 – 8 π SIZE or;

2. The registers Dym, Dyn respectively

Assembler TBLU. < size > < ea > ,Dx Result rounded

Syntax: TBLUN. < size > < ea > ,Dx Result not rounded

TBLU. < size > Dym:Dyn, Dx Result rounded

TBLUN. < size > Dym:Dyn, Dx Result not rounded

Attributes: Size = (Byte, Word, Long)

Description: The TBLU and TBLUN instructions allow the efﬁcient use of piecewise linear,

compressed data tables to model complex functions. The TBLU instruction has two

modes of operation: table lookup and interpolate mode and data register interpolate

mode.

For table lookup and interpolate mode, data register Dx 15 – 0 contains the

independent variable X. The effective address points to the start of a unsigned byte,

word, or long-word table containing a linearized representation of the dependent

variable, Y, as a function of X. In general, the independent variable, located in the low-

order word of Dx, consists of an 8-bit integer part and an 8-bit fractional part. An

assumed radix point is located between bits 7 and 8. The integer part, Dx 15 – 8, is

scaled by the operand size and is used as an offset into the table. The selected entry

in the table is subtracted from the next consecutive entry. A fractional portion of this

difference is taken by multiplying by the interpolation fraction, Dx 7 – 0. The adjusted

difference is then added to the selected table entry. The result is returned in the

destination data register, Dx.

CPU32 Instructions

7-12 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

TBLU TBLU

TBLUN Table Lookup and Interpolation (Unsigned) TBLUN

(CPU32)

For register interpolate mode, the interpolation occurs using the Dym and Dyn registers

in place of the two table entries. For this mode, only the fractional portion, Dx 7 – 0, is

used in the interpolation and the integer portion, Dx 15 – 8, is ignored. The register

interpolation mode may be used with several table lookup and interpolations to model

multidimensional functions.

Signed table entries range from – 2n – 1 to 2n – 1 – 1; whereas, unsigned table entries

range from 0 to 2n – 1 where n is 8, 16, or 32 for byte, word, and long-word tables,

respectively. The unsigned and unrounded table results will be zero-extended instead

of sign-extended.

Rounding of the result is optionally selected via the "R" instruction field. If R = 0

(TABLE), the fractional portion is rounded according to the round-to-nearest algorithm.

The rounding procedure can be summarized by the following table:

The adjusted difference is then added to the selected table entry. The rounded result

is returned in the destination data register, Dx. Only the portion of the register

corresponding to the selected size is affected.

If R = 1 (TBLUN), the result is returned in register Dx without rounding. If the size is

byte, the integer portion of the result is returned in Dx 15 – 8; the integer portion of a

word result is stored in Dx 23 – 8; the least significant 24 bits of a long result are stored

in Dx 31 – 8. Byte and word results are sign-extended to fill the entire 32-bit register.

Adjusted Difference

Fraction Rounding

Adjustme

≥ 1/2 + 1

< 1/2 + 0

31 24 23 16 15 8 7 0

BYTE UNAFFECTED UNAFFECTED UNAFFECTED RESULT

WORD UNAFFECTED UNAFFECTED RESULT RESULT

LONG RESULT RESULT RESULT RESULT

CPU32 Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 7-13

TBLU TBLU

TBLUN Table Lookup and Interpolation (Unsigned) TBLUN

(CPU32)

NOTE

The long-word result contains only the least signiﬁcant 24 bits of

integer precision.

For all sizes, the 8-bit fractional portion of the result is returned in the low byte of the

data register, Dx 7 – 0. User software can make use of the fractional data to reduce

cumulative errors in lengthy calculations or implement rounding algorithms different

from that provided by other forms of TBLU. The previously described assumed radix

point places two restrictions on the programmer:

1. Tables are limited to 257 entries in length.

2. Interpolation resolution is limited to 1/256, the distance between consecutive ta-

ble entries. The assumed radix point should not, however, be construed by the

programmer as a requirement that the independent variable be calculated as a

fractional number in the range 0 ≤ X ≤ 255. On the contrary, X should be consid-

ered to be an integer in the range 0 ≤ X ≤ 65535, realizing that the table is actu-

ally a compressed representation of a linearized function in which only every

256th value is actually stored in memory.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the result is set; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if the integer portion of an unrounded long result is not in the range, – (223)

≤ Result ≤ (223) – 1; cleared otherwise.

C — Always cleared.

31 24 23 16 15 8 7 0

BYTE SIGN-EXTENDED SIGN-EXTENDED RESULT FRACTION

WORD SIGN-EXTENDED RESULT RESULT FRACTION

LONG RESULT RESULT RESULT FRACTION

XNZVC

—∗∗∗0

CPU32 Instructions

7-14 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

TBLU TBLU

TBLUN Table Lookup and Interpolation (Unsigned) TBLUN

(CPU32)

Instruction Format:

TABLE LOOKUP AND INTERPOLATE

DATA REGISTER INTERPOLATE

Instruction Fields:

Effective address ﬁeld (table lookup and interpolate mode only)—Speciﬁes the

destination location. Only control alterable addressing modes are allowed as listed

in the following table:

Size ﬁeld—Speciﬁes the size of operation.

00 — Byte Operation

01 — Word Operation

10 — Long Operation

1514131211109876543210

1111100000 EFFECTIVE ADDRESS

MODE REGISTER

0 REGISTER Dx 0 R 0 1 SIZE 000000 0

1514131211109876543210

1111100000000 REGISTER Dym

0 REGISTER Dx 0 R 0 0 SIZE 0 0 0 REGISTER Dyn

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > — —

(An) + — —

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

CPU32 Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 7-15

TBLU TBLU

TBLUN Table Lookup and Interpolation (Unsigned) TBLUN

(CPU32)

contains the interpolation fraction and entry number.

Dym, Dyn ﬁeld—If the effective address mode ﬁeld is nonzero, this operand register is

unused and should be zero. If the effective address mode ﬁeld is zero, the surface

interpolation variant of this instruction is implied, and Dyn speciﬁes one of the two

source operands.

Rounding mode ﬁeld—The R-bit controls the rounding of the ﬁnal result. When R = 0,

the result is rounded according to the round-to-nearest algorithm. When R = 1,

the result is returned unrounded.