Floating Point Instructions

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FABS

Floating-Point Absolute Value

FABS

(MC6888X, MC68040)

Operation:

Absolute Value of Source

→

FPn

Assembler

Syntax:

FABS. < fmt > < ea > ,FPn

FABS.X FPm,FPn

FABS.X FPn

*FrABS. < fmt > < ea > ,FPn

*FrABS.X FPm,FPn

*FrABS.X Pn

where r is rounding precision, S or D

*Supported by MC68040 only.

Attributes:

Format = (Byte, Word, Long, Single, Quad, Extended, Packed)

Description:

Converts the source operand to extended precision (if necessary) and stores

the absolute value of that number in the destination ﬂoating-point data register.

FABS will round the result to the precision selected in the floating-point control register.

FSABS and FDABS will round the result to single or double precision, respectively,

regardless of the rounding precision selected in the floating-point control register.

Operation Table:

NOTE: If the source operand is a NAN, refer to

1.6.5 Not-A-Numbers

for more information

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result

Absolute Value Absolute Value Absolute Value

Floating Point Instructions

MOTOROLA

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FABS

Floating-Point Absolute Value

FABS

(MC6888X, MC68040)

Floating-Point Status Register:

Condition Codes: Affected as described in

3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to

1.6.5 Not-A-Numbers

OPERR Cleared

OVFL Cleared

UNFL If the source is an extended-precision

denormalized number, refer to exception

processing in the appropriate user’s manual;

cleared otherwise.

DZ Cleared

INEX2 Cleared

INEX1 If < fmt > is packed, refer to exception

processing in the appropriate user’s manual;

cleared otherwise.

Accrued Exception Byte: Affected as described in exception processing; refer to the

appropriate user’s manual.

Instruction Format:

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

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MOTOROLA

FABS

Floating-Point Absolute Value

FABS

(MC6888X, MC68040)

Instruction Fields:

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld speciﬁes the location of the source operand. Only data

addressing modes can be used as listed in the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA

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5-7

FABS

Floating-Point Absolute Value

FABS

(MC6888X, MC68040)

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)*

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

*This encoding will cause an unimplemented

data type exception in the MC68040 to allow emulation in software.

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

Opmode ﬁeld—Speciﬁes the instruction and rounding precision.

0011000 FABS Rounding precision speciﬁed by the ﬂoating-point control

1011000 FSABS Single-precision rounding speciﬁed.

1011100 FDABS Double-precision rounding speciﬁed.

Floating Point Instructions

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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

MOTOROLA

FACOS

Arc Cosine

FACOS

(MC6888X, M68040FPSP)

Operation:

Arc Cosine of Source

→

FPn

Assembler

FACOS. < fmt > < ea > ,FPn

Syntax:

FACOS.X FPm,FPn

FACOS.X FPn

Attributes:

Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description:

Converts the source operand to extended precision (if necessary) and

calculates the arc cosine of that number. Stores the result in the destination ﬂoating-

point data register. This function is not deﬁned for source operands outside of the range

[ – 1... + 1]; if the source is not in the correct range, a NAN is returned as the result and

the OPERR bit is set in the ﬂoating- point status register. If the source is in the correct

range, the result is in the range of [0...

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to

1.6.5 Not-A-Numbers

for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

Floating-Point Status Register:

Condition Codes: Affected as described in

3.6.2 Conditional Testing

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to

1.6.5 Not-A-Numbers

OPERR Set if the source is infinity, > + 1 or < – 1;

cleared otherwise.

OVFL Cleared

UNFL Cleared

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result

Arc Cosine +

/2 NAN

Floating Point Instructions

MOTOROLA

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FACOS

Arc Cosine

FACOS

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

MOTOROLA

FACOS

Arc Cosine

FACOS

(MC6888X, M68040FPSP)

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is then written

into the same register. If the single register syntax is used, Motorola assemblers

set the source and destination ﬁelds to the same value.

Floating Point Instructions

MOTOROLA

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5-11

FADD

Floating-Point Add

FADD

(MC6888X, MC68040)

Operation:

Source + FPn

→

FPn

Assembler FADD. < fmt > < ea > ,FPn

Syntax: FADD.X FPm,FPn

*FrADD. < fmt > < ea > ,FPn

*FrADD.X FPm,FPn

where r is rounding precision, S or D

*Supported by MC68040 only.

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and adds

that number to the number contained in the destination ﬂoating-point data register.

Stores the result in the destination ﬂoating-point data register.

FADD will round the result to the precision selected in the floating-point control register.

FSADD and FDADD will round the result to single or double-precision, respectively,

regardless of the rounding precision selected in the floating-point control register.

Operation Table:

1. If either operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Returns + 0.0 in rounding modes RN, RZ, and RP; returns – 0.0 in RM.

3. Sets the OPERR bit in the ﬂoating-point status register exception byte.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

In Range +

–Add Add + inf – inf

Zero +

–Add + 0.0 0.02

0.02 – 0.0 + inf – inf

Infinity +

–+ inf

– inf + inf

– inf + inf NAN3

NAN‡ – inf

Floating Point Instructions

5-12 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FADD Floating-Point Add FADD

(MC6888X, MC68040)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source and the destination are

opposite-signed infinities; cleared otherwise.

OVFL Refer to exception processing in the

appropriate user’s manual.

UNFL Refer to exception processing in the

appropriate user’s manual.

DZ Cleared

INEX2 Refer to exception processing in the

appropriate user’s manual.

INEX1 If < fmt > is packed, refer to exception

processing in the appropriate user’s manual;

cleared otherwise.

Accrued Exception Byte: Affected as described in exception processing in the appro-

priate user’s manual.

Instruction Format:

Instruction Fields:

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-13

FADD Floating-Point Add FADD

(MC6888X, MC68040)

If R/M = 1, speciﬁes the location of the source operand location. Only data

addressing modes can be used as listed in the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)*

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

*This encoding will cause an unimplemented data type exception to allow

emulation in software.

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

Opmode ﬁeld—Speciﬁes the instruction and rounding precision.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

0100010 FADD Rounding precision speciﬁed by the ﬂoating-point control

1100010 FSADD Single-precision rounding speciﬁed.

1100110 FDADD Double-precision rounding speciﬁed.

Floating Point Instructions

5-14 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FASIN Arc Sine FASIN

(MC6888X, M68040FPSP)

Operation: Arc Sine of the Source → FPn

Assembler FASIN. < fmt > < ea > ,FPn

Syntax: FASIN.X FPm,FPn

FASIN.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the arc sine of the number. Stores the result in the destination ﬂoating-point

data register. This function is not deﬁned for source operands outside of the range [ –

1... + 1]; if the source is not in the correct range, a NAN is returned as the result and

the OPERR bit is set in the ﬂoating- point status register. If the source is in the correct

range, the result is in the range of [ – π/2... + π/2].

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

Result Arc Sine + 0.0 – 0.0 NAN2

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-15

FASIN Arc Sine FASIN

(MC6888X, M68040FPSP)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source is infinity, > + 1 or < – 1;

cleared otherwise

OVFL Cleared

UNFL Can be set for an underflow condition.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-16 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FASIN Arc Sine FASIN

(MC6888X, M68040FPSP)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is then written

into the same register. If the single register syntax is used, Motorola assemblers

set the source and destination ﬁelds to the same value.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-17

FATAN Arc Tangent FATAN

(MC6888X, M68040FPSP)

Operation: Arc Tangent of Source → FPn

Assembler FATAN. < fmt > < ea > ,FPn

Syntax: FATAN.X FPm,FPn

FATAN.X FPm,FPnz

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the arc tangent of that number. Stores the result in the destination ﬂoating-

point data register. The result is in the range of [ – π/2... + π/2].

Operation Table:

NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Cleared

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result Arc Tangent + 0.0 – 0.0 + π/2 – π/2

Floating Point Instructions

5-18 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FATAN Arc Tangent FATAN

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-19

FATAN Arc Tangent FATAN

(MC6888X, M68040FPSP)

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is then written

into the same register. If the single register syntax is used, Motorola assemblers

set the source and destination ﬁelds to the same value.

Floating Point Instructions

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FATANH Hyperbolic Arc Tangent FATANH

(MC6888X, M68040FPSP)

Operation: Hyperbolic Arc Tangent of Source → FPn

Assembler FATANH. < fmt > < ea > ,FPn

Syntax: FATANH.X FPm,FPn

FATANH.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the hyperbolic arc tangent of that value. Stores the result in the destination

ﬂoating-point data register. This function is not deﬁned for source operands outside of

the range ( – 1... + 1); and the result is equal to – inﬁnity or + inﬁnity if the source is

equal to + 1 or – 1, respectively. If the source is outside of the range [ – 1... + 1], a NAN

is returned as the result, and the OPERR bit is set in the ﬂoating-point status register.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

Result Hyperbolic

Arc Tangent + 0.0 – 0.0 NAN2

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-21

FATANH Hyperbolic Arc Tangent FATANH

(MC6888X, M68040FPSP)

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source is > + 1 or < – 1; cleared

otherwise.

OVFL Cleared

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Set if the source is equal to + 1 or – 1; cleared

otherwise.

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-22 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FATANH Hyperbolic Arc Tangent FATANH

(MC6888X, M68040FPSP)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is then written

into the same register. If the single register syntax is used, Motorola assemblers

set the source and destination ﬁelds to the same value.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-23

FBcc Floating-Point Branch Conditionally FBcc

(MC6888X, MC68040)

Operation: If Condition True

Then PC + dn → PC

Assembler:

Syntax: FBcc. < size > , < label >

Attributes: Size = (Word, Long)

Description: If the speciﬁed ﬂoating-point condition is met, program execution continues at

the location (PC) + displacement. The displacement is a twos-complement integer that

counts the relative distance in bytes. The value of the program counter used to

calculate the destination address is the address of the branch instruction plus two. If

the displacement size is word, then a 16- bit displacement is stored in the word

immediately following the instruction operation word. If the displacement size is long

word, then a 32-bit displacement is stored in the two words immediately following the

instruction operation word. The conditional speciﬁer cc selects any one of the 32

ﬂoating- point conditional tests as described in 3.6.2 Conditional Testing.

Floating-Point Status Register:

Condition Codes: Not affected.

Quotient Byte: Not affected.

Exception Byte: BSUN Set if the NAN condition code is set and the

condition selected is an IEEE nonaware test.

SNAN Not Affected.

OPERR Not Affected.

OVF Not Affected.

UNFL Not Affected.

DZ Not Affected.

INEX2 Not Affected.

INEX1 Not Affected.

Accrued Exception Byte: The IOP bit is set if the BSUN bit is set in the exception

byte. No other bit is affected.

Floating Point Instructions

5-24 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FBcc Floating-Point Branch Conditionally FBcc

(MC6888X, MC68040)

Instruction Format:

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the signed displacement.

If Format = 0, then the displacement is 16 bits and is sign- extended before use.

If Format = 1, then the displacement is 32 bits.

Conditional Predicate ﬁeld—Speciﬁes one of 32 conditional tests as deﬁned in Table

3-23 Floating-Point Conditional Tests.

NOTE

When a BSUN exception occurs, the main processor takes a

preinstruction exception. If the exception handler returns without

modifying the image of the program counter on the stack frame

(to point to the instruction following the FBcc), then it must clear

the cause of the exception (by clearing the NAN bit or disabling

the BSUN trap), or the exception will occur again immediately

upon return to the routine that caused the exception.

1514131211109876543210

1111COPROCESSOR

ID 0 1 SIZE CONDITIONAL PREDICATE

16-BIT DISPLACEMENT OR MOST SIGNIFICANT WORD OF 32-BITDISPLACEMENT

LEAST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT (IF NEEDED)

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-25

FCMP Floating-Point Compare FCMP

(MC6888X, MC68040)

Operation: FPn – Source

Assembler FCMP. < fmt > < ea > ,FPn

Syntax: FCMP.X FPm,FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

subtracts the operand from the destination ﬂoating- point data register. The result of the

subtraction is not retained, but it is used to set the ﬂoating-point condition codes as

described in 3.6.2 Conditional Testing.

Operation Table: The entries in this operation table differ from those of the tables

describing most of the ﬂoating-point instructions. For each combination of input

operand types, the condition code bits that may be set are indicated. If the name of a

condition code bit is given and is not enclosed in brackets, then it is always set. If the

name of a condition code bit is enclosed in brackets, then that bit is either set or

cleared, as appropriate. If the name of a condition code bit is not given, then that bit is

always cleared by the operation. The inﬁnity bit is always cleared by the FCMP

instruction since it is not used by any of the conditional predicate equations. Note that

the NAN bit is not shown since NANs are always handled in the same manner (as

described in 1.6.5 Not-A-Numbers).

NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

In Range +

–{NZ} none

N {NZ} none none

N N

N none

Zero +

–N none

N none Z Z

NZ NZ N none

N none

Infinity +

–none none

N N none none

N N Z none

N NZ

Floating Point Instructions

5-26 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FCMP Floating-Point Compare FCMP

(MC6888X, MC68040)

Floating-Point Status Register:

Condition Codes: Affected as described in the preceding operation table.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Cleared

UNFL Cleared

DZ Cleared

INEX2 Cleared

INEX1 If < fmt > is packed, refer to exception

processing in the appropriate user’s manual;

cleared otherwise.

Accrued Exception Byte: Affected as described in exception processing in the appro-

priate user’s manual.

Instruction Format:

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-27

FCMP Floating-Point Compare FCMP

(MC6888X, MC68040)

Instruction Fields:

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, speciﬁes the location of the source operand location. Only data

addressing modes can be used as listed in the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)*

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

*This encoding in the MC68040 will cause an unimplemented data type

exception to allow emulation in software.

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-28 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FCOS Cosine FCOS

(MC6888X, M68040FPSP)

Operation: Cosine of Source → FPn

Assembler FCOS. < fmt > < ea > ,FPn

Syntax: FCOS.X FPm,FPn FCOS.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the cosine of that number. Stores the result in the destination ﬂoating-point

data register. This function is not deﬁned for source operands of ± inﬁnity. If the source

operand is not in the range of [ – 2π... + 2π], then the argument is reduced to within that

range before the cosine is calculated. However, large arguments may lose accuracy

during reduction, and very large arguments (greater than approximately 1020) lose all

accuracy. The result is in the range of [ – 1... + 1].

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

Result Cosine + 1.0 NAN2

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-29

FCOS Cosine FCOS

(MC6888X, M68040FPSP)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source operand is ± infinity; cleared

otherwise.

OVFL Cleared

UNFL Cleared

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-30 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FCOS Cosine FCOS

(MC6888X, M68040FPSP)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should contain zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-31

FCOSH Hyperbolic Cosine FCOSH

(MC6888X, M68040FPSP)

Operation: Hyperbolic Cosine of Source → FPn

Assembler FCOSH. < fmt > < ea > ,FPn

Syntax: FCOSH.X FPm,FPn FCOSH.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the hyperbolic cosine of that number. Stores the result in the destination

ﬂoating-point data register.

Operation Table:

NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Refer to overflow in the appropriate user’s

manual.

UNFL Cleared

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result Hyperbolic Cosine + 1.0 + inf

Floating Point Instructions

5-32 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FCOSH Hyperbolic Cosine FCOSH

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-33

FCOSH Hyperbolic Cosine FCOSH

(MC6888X, M68040FPSP)

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Floating Point Instructions

5-34 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FDBcc Floating-Point Test Condition, FDBcc

Decrement, and Branch

(MC6888X, MC68040)

Operation: If Condition True

Then No Operation

Else Dn – 1 → Dn

If Dn ≠ – 1

Then PC + dn → PC

Else Execute Next Instruction

Assembler

Syntax: FDBcc Dn, < label >

Attributes: Unsized

Description: This instruction is a looping primitive of three parameters: a ﬂoating-point

condition, a counter (data register), and a 16-bit displacement. The instruction ﬁrst tests

the condition to determine if the termination condition for the loop has been met, and if

so, execution continues with the next instruction in the instruction stream. If the

termination condition is not true, the low-order 16 bits of the counter register are

decremented by one. If the result is – 1, the count is exhausted, and execution

continues with the next instruction. If the result is not equal to – 1, execution continues

at the location speciﬁed by the current value of the program counter plus the sign-

extended 16-bit displacement. The value of the program counter used in the branch

address calculation is the address of the displacement word.

The conditional specifier cc selects any one of the 32 floating- point conditional tests

as described in 3.6.2 Conditional Testing.

Floating-Point Status Register:

Condition Codes: Not affected.

Quotient Byte: Not affected.

Exception Byte: BSUN Set if the NAN condition code is set and the

condition selected is an IEEE nonaware test.

SNAN Not Affected.

OPERR Not Affected.

OVFL Not Affected.

UNFL Not Affected.

DZ Not Affected.

NEX2 Not Affected.

INEX1 Not Affected.

Accrued Exception Byte: The IOP bit is set if the BSUN bit is set in the exception

byte. No other bit is affected.

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-35

FDBcc Floating-Point Test Condition, FDBcc

Decrement, and Branch

(MC6888X, MC68040)

Instruction Format:

Instruction Fields:

Count Register ﬁeld—Speciﬁes data register that is used as the counter.

Conditional Predicate ﬁeld—Speciﬁes one of the 32 ﬂoating-point conditional tests as

described in 3.6.2 Conditional Testing.

Displacement ﬁeld—Speciﬁes the branch distance (from the address of the instruction

plus two) to the destination in bytes.

NOTE

The terminating condition is like that deﬁned by the UNTIL loop

constructs of high-level languages. For example: FDBOLT can

be stated as "decrement and branch until ordered less than".

There are two basic ways of entering a loop: at the beginning or

by branching to the trailing FDBcc instruction. If a loop structure

terminated with FDBcc is entered at the beginning, the control

counter must be one less than the number of loop executions

desired. This count is useful for indexed addressing modes and

dynamically speciﬁed bit operations. However, when entering a

loop by branching directly to the trailing FDBcc instruction, the

count should equal the loop execution count. In this case, if the

counter is zero when the loop is entered, the FDBcc instruction

does not branch, causing a complete bypass of the main loop.

When a BSUN exception occurs, a preinstruction exception is

taken by the main processor. If the exception handler returns

without modifying the image of the program counter on the stack

frame (to point to the instruction following the FDBcc), then it

must clear the cause of the exception (by clearing the NAN bit or

disabling the BSUN trap), or the exception will occur again im-

mediately upon return to the routine that caused the exception.

1514131211109876543210

1111COPROCESSOR

ID 001001 COUNT

0000000000 CONDITIONAL PREDICATE

16-BIT DISPLACEMENT

Floating Point Instructions

5-36 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FDIV Floating-Point Divide FDIV

(MC6888X, MC68040)

Operation: FPn ÷ Source → FPn

Assembler FDIV. < fmt > < ea > ,FPn

Syntax: FDIV.X FPm,FPn

*FrDIV. < fmt > < ea > ,FPn

*FrDIV.X FPm,FPn

where r is rounding precision, S or D

*Supported by MC68040 only

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and divides

that number into the number in the destination ﬂoating-point data register. Stores the

result in the destination ﬂoating-point data register.

FDIV will round the result to the precision selected in the floating-point control register.

FSDIV and FDDIV will round the result to single or double precision, respectively,

regardless of the rounding precision selected in the floating-point control register.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the DZ bit in the ﬂoating-point status register exception byte.

3. Sets the OPERR bit in the ﬂoating-point status register exception byte.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

In Range +

–Divide + inf2 – inf2

– inf2 + inf2+ 0.0 – 0.0

– 0.0 + 0.0

Zero +

–+ 0.0 + 0.0

– 0.0 + 0.0 NAN3+ 0.0 – 0.0

– 0.0 + 0.0

Infinity +

–+ inf – inf

– inf + inf + inf – inf

– inf + inf NAN‡

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-37

FDIV Floating-Point Divide FDIV

(MC6888X, MC68040)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set for 0 ÷ 0 or infinity ÷ infinity; cleared

otherwise.

OVFL Refer to exception processing in the

appropriate user’s manual.

UNFL Refer to exception processing in the

appropriate user’s manual.

DZ Set if the source is zero and the destination is

in range; cleared otherwise.

INEX2 Refer to exception processing in the

appropriate user’s manual.

INEX1 If < fmt > is packed, refer to exception

processing in the appropriate user’s manual;

cleared otherwise.

Accrued Exception Byte: Affected as described in exception processing in the appro-

priate user’s manual.

Instruction Format:

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-38 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FDIV Floating-Point Divide FDIV

(MC6888X, MC68040)

Instruction Fields:

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, speciﬁes the location of the source operand location. Only data

addressing modes can be used as listed in the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)*

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

*This encoding in the MC68040 will cause an unimplemented data type

exception to allow emulation in software.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-39

FDIV Floating-Point Divide FDIV

(MC6888X, MC68040)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

Opmode ﬁeld—Speciﬁes the instruction and rounding precision.

0100000 FDIV Rounding precision speciﬁed by the ﬂoating- point

control register.

1100000 FSDIV Single-precision rounding speciﬁed.

1100100 FDDIV Double-precision rounding speciﬁed.

Floating Point Instructions

5-40 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FETOX exFETOX

(MC6888X, M68040FPSP)

Operation: eSource → FPn

Assembler FETOX. < fmt > < ea > ,FPn

Syntax: FETOX.X FPm,FPn

Syntax: FETOX.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates e to the power of that number. Stores the result in the destination ﬂoating-

point data register.

Operation Table:

NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Refer to overflow in the appropriate user’s

manual.

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result ex+ 1.0 + inf + 0.0

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-41

FETOX exFETOX

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-42 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FETOX exFETOX

(MC6888X, M68040FPSP)

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer Field—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)*

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-43

FETOXM1 ex – 1 FETOXM1

(MC6888X, M68040FPSP)

Operation: eSource – 1 → FPn

Assembler FETOXM1. < fmt > < ea > ,FPn

Syntax: FETOXM1.X FPm,FPn

FETOXM1.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates e to the power of that number. Subtracts one from the value and stores the

result in the destination ﬂoating-point data register.

Operation Table:

NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Refer to overflow in the appropriate user’s

manual.

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result ex – 1 + 0.0 – 0.0 + inf – 1.0

Floating Point Instructions

5-44 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FETOXM1 ex – 1 FETOXM1

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-45

FETOXM1 ex – 1 FETOXM1

(MC6888X, M68040FPSP)

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer Field—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Floating Point Instructions

5-46 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FGETEXP Get Exponent FGETEXP

(MC6888X, M68040FPSP)

Operation: Exponent of Source → FPn

Assembler FGETEXP. < fmt > < ea > ,FPn

Syntax: FGETEXP.X FPm,FPn

FGETEXP.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

extracts the binary exponent. Removes the exponent bias, converts the exponent to an

extended-precision ﬂoating- point number, and stores the result in the destination

ﬂoating- point data register.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source is ± infinity; cleared

otherwise.

OVFL Cleared

UNFL Cleared

DZ Cleared

INEX2 Cleared

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

Result Exponent + 0.0 – 0.0 NAN2

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-47

FGETEXP Get Exponent FGETEXP

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-48 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FGETEXP Get Exponent FGETEXP

(MC6888X, M68040FPSP)

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-49

FGETMAN Get Mantissa FGETMAN

(MC6888X, M68040FPSP)

Operation: Mantissa of Source → FPn

Assembler FGETMAN. < fmt > < ea > ,FPn

Syntax: FGETMAN.X FPm,FPn

FGETMAN.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

extracts the mantissa. Converts the mantissa to an extended-precision value and

stores the result in the destination ﬂoating-point data register. The result is in the range

[1.0...2.0] with the sign of the source mantissa, zero, or a NAN.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source is ± infinity; cleared

otherwise.

OVFL Cleared

UNFL Cleared

DZ Cleared

INEX2 Cleared

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

Result Mantissa + 0.0 – 0.0 NAN2

Floating Point Instructions

5-50 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FGETMAN Get Mantissa FGETMAN

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-51

FGETMAN Get Mantissa FGETMAN

(MC6888X, M68040FPSP)

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Floating Point Instructions

5-52 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FINT Integer Part FINT

(MC6888X, M68040FPSP)

Operation: Integer Part of Source → FPn

Assembler FINT. < fmt > < ea > ,FPn

Syntax: FINT.X FPm,FPn

FINT.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary), extracts

the integer part, and converts it to an extended-precision ﬂoating-point number. Stores

the result in the destination ﬂoating-point data register. The integer part is extracted by

rounding the extended-precision number to an integer using the current rounding mode

selected in the ﬂoating-point control register mode control byte. Thus, the integer part

returned is the number that is to the left of the radix point when the exponent is zero,

after rounding. For example, the integer part of 137.57 is 137.0 for the round-to-zero

and round-to- negative inﬁnity modes and 138.0 for the round-to-nearest and round-to-

positive inﬁnity modes. Note that the result of this operation is a ﬂoating-point number.

Operation Table:

NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result Integer + 0.0 – 0.0 + inf – inf

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-53

FINT Integer Part FINT

(MC6888X, M68040FPSP)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Cleared

UNFL Cleared

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-54 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FINT Integer Part FINT

(MC6888X, M68040FPSP)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-55

FINTRZ Integer Part, Round-to-Zero FINTRZ

(MC6888X, M68040FPSP)

Operation: Integer Part of Source → FPn

Assembler FINTRZ. < fmt > < ea > ,FPn

Syntax: FINTRZ.X FPm,FPn

FINTRZ.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

extracts the integer part and converts it to an extended-precision ﬂoating-point number.

Stores the result in the destination ﬂoating-point data register. The integer part is

extracted by rounding the extended-precision number to an integer using the round-to-

zero mode, regardless of the rounding mode selected in the ﬂoating-point control

integer part returned is the number that is to the left of the radix point when the

exponent is zero. For example, the integer part of 137.57 is 137.0; the integer part of

0.1245 x 102 is 12.0. Note that the result of this operation is a ﬂoating-point number.

Operation Table:

NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result Integer, Forced

Round-to- Zero + 0.0 – 0.0 + inf – inf

Floating Point Instructions

5-56 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FINTRZ Integer Part, Round-to-Zero FINTRZ

(MC6888X, M68040FPSP)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Cleared

UNFL Cleared

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-57

FINTRZ Integer Part, Round-to-Zero FINTRZ

(MC6888X, M68040FPSP)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If RM = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-58 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FLOG10 Log10 FLOG10

(MC6888X, M68040FPSP)

Operation: Log10 of Source → FPn

Assembler FLOG10. < fmt > < ea > ,FPn

Syntax: FLOG10.X FPm,FPn

FLOG10.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Convert the source operand to extended precision (if necessary) and

calculates the logarithm of that number using base 10 arithmetic. Stores the result in

the destination ﬂoating-point data register. This function is not deﬁned for input values

less than zero.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

3. Sets the DZ bit in the ﬂoating-point status register exception byte.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source operand is < 0; cleared

otherwise.

OVFL Cleared

UNFL Cleared

DZ Set if the source is ± 0; cleared otherwise

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

Result Log10 NAN2– inf3+ inf NAN2

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-59

FLOG10 Log10 FLOG10

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-60 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FLOG10 Log10 FLOG10

(MC6888X, M68040FPSP)

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-61

FLOG2 Log2FLOG2

(MC6888X, M68040FPSP)

Operation: Log2 of Source → FPn

Assembler FLOG2. < fmt > < ea > ,FPn

Syntax: FLOG2.X FPm,FPn

FLOG2.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the logarithm of that number using base two arithmetic. Stores the result in

the destination ﬂoating- point data register. This function is not deﬁned for input values

less than zero.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

3. Sets the DZ bit in the ﬂoating-point status register exception byte.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source is < 0; cleared otherwise

OVFL Cleared

UNFL Cleared

DZ Set if the source is ± 0; cleared otherwise

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

Result Log2 NAN2– inf3+ inf NAN2

Floating Point Instructions

5-62 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FLOG2 Log2FLOG2

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-63

FLOG2 Log2FLOG2

(MC6888X, M68040FPSP)

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Floating Point Instructions

5-64 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FLOGN LogeFLOGN

(MC6888X, M68040FPSP)

Operation: Loge of Source → FPn

Assembler FLOGN. < fmt > < ea > ,FPn

Syntax: FLOGN.X FPm,FPn

FLOGN.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the natural logarithm of that number. Stores the result in the destination

ﬂoating-point data register. This function is not deﬁned for input values less than zero.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

3. Sets the DZ bit in the ﬂoating-point status register exception byte.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source operand is < 0; cleared

otherwise.

OVFL Cleared

UNFL Cleared

DZ Set if the source is ± 0; cleared otherwise

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

Result In(x) NAN2– inf3+ inf NAN2

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-65

FLOGN LogeFLOGN

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-66 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FLOGN LogeFLOGN

(MC6888X, M68040FPSP)

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-67

FLOGNP1 Loge (x + 1) FLOGNP1

(MC6888X, M68040FPSP)

Operation: Loge of (Source + 1) → FPn

Assembler FLOGNP1. < fmt > < ea > ,FPn

Syntax: FLOGNP1.X FPm,FPn

FLOGNP1.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary), adds one

to that value, and calculates the natural logarithm of that intermediate result. Stores the

result in the destination ﬂoating-point data register. This function is not deﬁned for input

values less than – 1.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. If the source is – 1, sets the DZ bit in the ﬂoating-point status register

exception byte and returns a NAN. If the source is < – 1, sets the OPERR bit

in the ﬂoating-point status register exception byte and returns a NAN.

3. Sets the OPERR bit in the ﬂoating-point status register exception byte.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

Result In(x + 1) In(x + 1)2+ 0.0 – 0.0 + inf NAN23

Floating Point Instructions

5-68 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FLOGNP1 Loge (x + 1) FLOGNP1

(MC6888X, M68040FPSP)

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source operand is < – 1; cleared

otherwise.

OVFL Cleared

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Set if the source operand is – 1; cleared

otherwise

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-69

FLOGNP1 Loge (x + 1) FLOGNP1

(MC6888X, M68040FPSP)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-70 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMOD Modulo Remainder FMOD

(MC6888X, M68040FPSP)

Operation: Modulo Remainder of (FPn ÷ Source) → FPn

Assembler FMOD. < fmt > < ea > ,FPn

Syntax: FMOD.X FPm,FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the modulo remainder of the number in the destination ﬂoating-point data

ﬂoating-point data register and stores the sign and seven least signiﬁcant bits of the

quotient in the ﬂoating-point status register quotient byte (the quotient is the result of

FPn ÷ Source). The modulo remainder function is deﬁned as:

FPn – (Source x N)

where N = INT(FPn ÷ Source) in the round-to-zero mode.

The FMOD function is not deﬁned for a source operand equal to zero or for a destination

operand equal to inﬁnity. Note that this function is not the same as the FREM instruction,

which uses the round-to-nearest mode and thus returns the remainder that is required by

the IEEE

Speciﬁcation for Binary Floating-Point Arithmetic

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

3. Returns the value of FPn before the operation. However, the result is

processed by the normal instruction termination procedure to round it as

required. Thus, an overﬂow and/or inexact result may occur if the rounding

precision has been changed to a smaller size since the FPn value was

loaded

DESTINATION SOURCE1

+ In Range – + Zero# – + Inﬁnity –

In Range +

–Modulo Remainder NAN2FPn3

Zero +

–+ 0.0

– 0.0 NAN2+ 0.0

– 0.0

Infinity +

–NAN2NAN2NAN2

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-71

FMOD Modulo Remainder FMOD

(MC6888X, M68040FPSP)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Loaded with the sign and least significant seven bits of the

quotient (FPn ÷ Source). The sign of the quotient is the

exclusive-OR of the sign bits of the source and destination

operands.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source is zero or the destination is

infinity; cleared otherwise.

OVFL Cleared

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, in the appropriate user’s

manual for inexact result on decimal input;

cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-72 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMOD Modulo Remainder FMOD

(MC6888X, M68040FPSP)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-73

FMOVE Move Floating-Point Data Register FMOVE

(MC6888X, MC68040)

Operation: Source → Destination

Assembler FMOVE. < fmt > < ea > ,FPn

Syntax: FMOVE. < fmt > FPm, < ea >

FMOVE.P FPm, < ea > {Dn}

FMOVE.P FPm, < ea > {k}

*FrMOVE. < fmt > < ea > ,FPn

where r is rounding precision, S or D

*Supported by MC68040 only

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Moves the contents of the source operand to the destination operand.

Although the primary function of this instruction is data movement, it is also considered

an arithmetic instruction since conversions from the source operand format to the

destination operand format are performed implicitly during the move operation. Also,

the source operand is rounded according to the selected rounding precision and mode.

Unlike the MOVE instruction, the FMOVE instruction does not support a memory-to-

memory format. For such transfers, it is much faster to utilize the MOVE instruction to

transfer the floating- point data than to use the FMOVE instruction. The FMOVE

instruction only supports memory-to-register, register-to- register, and register-to-

memory operations (in this context, memory may refer to an integer data register if the

data format is byte, word, long, or single). The memory-to-register and register- to-reg-

ister operation uses a command word encoding distinctly different from that used by

the register-to-memory operation; these two operation classes are described sepa-

rately.

Memory-to-Register and Register-to-Register Operation: Converts the source operand

to an extended-precision ﬂoating-point number (if necessary) and stores it in the

destination ﬂoating-point data register. MOVE will round the result to the precision

selected in the ﬂoating-point control register. FSMOVE and FDMOVE will round the

result to single or double precision, respectively, regardless of the rounding precision

selected in the ﬂoating-point control register. Depending on the source data format and

the rounding precision, some operations may produce an inexact result. In the following

table, combinations that can produce an inexact result are marked with a dot (⋅), but all

other combinations produce an exact result.

Floating Point Instructions

5-74 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMOVE Move Floating-Point Data Register FMOVE

(MC6888X, MC68040)

Floating-Point Status Register ( < ea > to Register):

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Cleared

UNFL Refer to exception processing in the

appropriate user’s manual if the source is an

extended-precision denormalized number;

cleared otherwise.

DZ Cleared

INEX2 Refer to exception processing in the

appropriate user’s manual if < fmt > is L,D, or

X; cleared otherwise.

INEX1 Refer to exception processing in the

appropriate user’s manual if < fmt > is P;

cleared otherwise.

Accrued Exception Byte: Affected as described in exception processing in the appro-

priate user’s manual.

Rounding

Precision Source Format

BWLSDXP

Single ⋅ ⋅⋅⋅

Double ⋅⋅

Extended ⋅

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-75

FMOVE Move Floating-Point Data Register FMOVE

(MC6888X, MC68040)

Instruction Format:

< EA > TO REGISTER

Instruction Fields:

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, speciﬁes the location of the source operand. Only data addressing modes

can be used as listed in the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-76 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMOVE Move Floating-Point Data Register FMOVE

(MC6888X, MC68040)

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)*

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

*This encoding in the MC68040 will cause an unimplemented data type

exception to allow emulation in software.

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

Opmode ﬁeld—Speciﬁes the instruction and rounding precision.

destination format and stores it at the destination effective address. If the format of the

destination is packed decimal, a third operand is required to specify the format of the

resultant string. This operand, called the k-factor, is a 7-bit signed integer (twos

complement) and may be speciﬁed as an immediate value or in an integer data

used, and the rest of the register is ignored.

0000000 FMOVE Rounding precision speciﬁed by the ﬂoating-point

control register.

1000000 FSMOVE Single-precision rounding speciﬁed.

1000100 FDMOVE Double-precision rounding speciﬁed.

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-77

FMOVE Move Floating-Point Data Register FMOVE

(MC6888X, MC68040)

Floating-Point Status Register (Register-to-Memory):

Condition Codes: Not affected.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

< fmt > is B, W, or L SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source operand is infinity or if the

destination size is exceeded after conversion

and rounding; cleared otherwise.

OVFL Cleared

UNFL Cleared

DZ Cleared

INEX2 Refer to exception processing in the

appropriate user’s manual.

INEX1 Cleared

< fmt > is S, D, or X BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers

OVFL Refer to exception processing in the

appropriate user’s manual.

UNFL Refer to exception processing in the

appropriate user’s manual.

DZ Cleared

INEX2 Refer to exception processing in the

appropriate user’s manual.

INEX1 Cleared

< fmt > is P BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the k-factor > + 17 or the magnitude of

the decimal exponent exceeds three digits;

cleared otherwise.

OVFL Cleared

UNFL Cleared

DZ Cleared

INEX2 Refer to exception processing in the

appropriate user’s manual.

INEX1 Cleared

Accrued Exception Byte: Affected as described in exception processing in the appro-

priate user’s manual.

Floating Point Instructions

5-78 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMOVE Move Floating-Point Data Register FMOVE

(MC6888X, MC68040)

Instruction Format:

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the destination location. Only data alterable

addressing modes can be used as listed in the following table:

*Only if < fmt > is byte, word, long, or single.

Destination Format ﬁeld—Speciﬁes the data format of the destination operand:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real with Static k-Factor (P{#k})*

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

111 —Packed-Decimal Real with Dynamic k-Factor (P{Dn})*

*This encoding will cause an unimplemented data type exception in the

MC68040 to allow emulation in software.

1514131211109876543210

111COPROCESSOR

ID 1000 EFFECTIVE ADDRESS

MODE REGISTER

011 DESTINATION

FORMAT SOURCE

(IF REQUIRED)

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) — —

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) — —

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-79

FMOVE Move Floating-Point Data Register FMOVE

(MC6888X, MC68040)

Source Register ﬁeld—Speciﬁes the source ﬂoating-point data register.

k-Factor ﬁeld—If the destination format is packed decimal, used to specify the format

of the decimal string. For any other destination format, this ﬁeld should be set to

all zeros. For a static k-factor, this ﬁeld is encoded with a twos-complement

integer where the value deﬁnes the format as follows:

– 64 to 0—Indicates the number of signiﬁcant digits to the right of the decimal

point (FORTRAN "F" format).

+ 1 to + 17—Indicates the number of signiﬁcant digits in the mantissa (FOR-

TRAN "E" format).

+ 18 to + 63—Sets the OPERR bit in the ﬂoating-point status register exception

byte and treated as + 17.

The format of this field for a dynamic k-factor is:

r r r 0 0 0 0

where "rrr" is the number of the main processor data register that contains the k-factor

value.

The following table gives several examples of how the k-factor value affects the format

of the decimal string that is produced by the floating-point coprocessor. The format of

the string that is generated is independent of the source of the k-factor (static or

dynamic).

k- Factor Source Operand Value Destination String

– 5 + 12345.678765 + 1.234567877E + 4

– 3 + 12345.678765 + 1.2345679E + 4

– 1 + 12345.678765 + 1.23457E + 4

0 + 12345.678765 + 1.2346E + 4

+ 1 + 12345.678765 + 1.E + 4

+ 3 + 12345.678765 + 1.23E + 4

+ 5 + 12345.678765 + 1.2346E + 4

Floating Point Instructions

5-80 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMOVE Move Floating-Point FMOVE

System Control Register

(MC6888X, MC68040)

Operation: Source → Destination

Assembler FMOVE.L < ea > ,FPCR

Syntax: FMOVE.L FPCR, < ea >

Attributes: Size = (Long)

Description: Moves the contents of a ﬂoating-point system control register (ﬂoating-point

control register, ﬂoating-point status register, or ﬂoating-point instruction address

though the system control register may not have 32 implemented bits. Unimplemented

bits of a control register are read as zeros and are ignored during writes (must be zero

for compatibility with future devices). For the MC68881, this instruction does not cause

pending exceptions (other than protocol violations) to be reported. Furthermore, a write

to the ﬂoating-point control register exception enable byte or the ﬂoating-point status

value written.

Floating-Point Status Register: Changed only if the destination is the ﬂoating-point status

Instruction Format:

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

10dr REGISTER

SELECT 0000000000

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-81

FMOVE Move Floating-Point FMOVE

System Control Register

(MC6888X, MC68040)

Instruction Fields:

Effective Address ﬁeld—(Memory-to-Register) All addressing modes can be used as

listed in the following table:

*Only if the source register is the ﬂoating-point instruction address register.

Effective Address ﬁeld—(Register-to-Memory) Only alterable addressing modes can

be used as listed in the following table:

*Only if the source register is the ﬂoating-point instruction address register.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An* 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An* 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An # < data > — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) — —

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) — —

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Floating Point Instructions

5-82 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMOVE Move Floating-Point FMOVE

System Control Register

(MC6888X, MC68040)

dr ﬁeld—Speciﬁes the direction of the data transfer.

0 — From < ea > to the speciﬁed system control register.

1 — From the speciﬁed system control register to < ea > .

100 Floating-Point Control Register

010 Floating-Point Status Register

001 Floating-Point Instruction Address Register

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-83

FMOVECR Move Constant ROM FMOVECR

(MC6888X, M68040FPSP)

Operation: ROM Constant → FPn

Assembler

Syntax: FMOVECR.X # < ccc > ,FPn

Attributes: Format = (Extended)

Description: Fetches an extended-precision constant from the ﬂoating- point coprocessor

on-chip ROM, rounds the mantissa to the precision speciﬁed in the ﬂoating-point

control register mode control byte, and stores it in the destination ﬂoating-point data

values of the constants contained in the ROM are shown in the offset table at the end

of this description.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Cleared

OPERR Cleared

OVFL Cleared

UNFL Cleared

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 Cleared

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

1514131211109876543210

1111COPROCESSOR

ID 000000000

010111 DESTINATION

Floating Point Instructions

5-84 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMOVECR Move Constant ROM FMOVECR

(MC6888X, M68040FPSP)

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

ROM Offset ﬁeld—Speciﬁes the offset into the ﬂoating-point coprocessor on-chip

constant ROM where the desired constant is located. The offsets for the available

constants are as follows:

The on-chip ROM contains other constants useful only to the on- chip microcode rou-

tines. The values contained at offsets other than those defined above are reserved for

the use of Motorola and may be different on various mask sets of the floating-point

coprocessor. These undefined values yield the value 0.0 in the M68040FPSP.

Offset Constant

$00 π

$0B Log10(2)

$0C e

$0D Log2(e)

$0E Log10(e)

$0F 0.0

$30 1n(2)

$31 1n(10)

$32 100

$33 101

$34 102

$35 104

$36 108

$37 1016

$38 1032

$39 1064

$3A 10128

$3B 10256

$3C 10512

$3D 101024

$3E 102048

$3F 104096

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-85

FMOVEM Move Multiple Floating-Point FMOVEM

Data Registers

(MC6888X, MC68040)

Operation: Register List → Destination

Source → Register List

Assembler FMOVEM.X < list > , < ea >

Syntax: FMOVEM.X Dn, < ea >

FMOVEM.X < ea > , < list > FMOVEM.X < ea > ,Dn

Attributes: Format = (Extended)

Description:Moves one or more extended-precision numbers to or from a list of ﬂoating-

point data registers. No conversion or rounding is performed during this operation, and

the ﬂoating-point status register is not affected by the instruction. For the MC68881, this

instruction does not cause pending exceptions (other than protocol violations) to be

reported. Furthermore, a write to the ﬂoating- point control register exception enable

byte or the ﬂoating-point status register exception status byte connot generate a new

exception, despite the value written.

Any combination of the eight floating-point data registers can be transferred, with the

selected registers specified by a user- supplied mask. This mask is an 8-bit number,

where each bit corresponds to one register; if a bit is set in the mask, that register is

moved. The register select mask may be specified as a static value contained in the

instruction or a dynamic value in the least significant eight bits of an integer data reg-

ister (the remaining bits of the register are ignored).

FMOVEM allows three types of addressing modes: the control modes, the predecre-

ment mode, or the postincrement mode. If the effective address is one of the control

addressing modes, the registers are transferred between the processor and memory

starting at the specified address and up through higher addresses. The order of the

transfer is from FP0 – FP7.

Floating Point Instructions

5-86 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMOVEM Move Multiple Floating-Point FMOVEM

Data Registers

(MC6888X, MC68040)

If the effective address is the predecrement mode, only a register- to-memory opera-

tion is allowed. The registers are stored starting at the address contained in the

address register and down through lower addresses. Before each register is stored, the

address register is decremented by 12 (the size of an extended-precision number in

memory) and the floating-point data register is then stored at the resultant address.

When the operation is complete, the address register points to the image of the last

floating- point data register stored. The order of the transfer is from FP7 – FP0.

If the effective address is the postincrement mode, only a memory- to-register opera-

tion is allowed. The registers are loaded starting at the specified address and up

through higher addresses. After each register is stored, the address register is incre-

mented by 12 (the size of an extended-precision number in memory). When the oper-

ation is complete, the address register points to the byte immediately following the

image of the last floating-point data register loaded. The order of the transfer is the

same as for the control addressing modes: FP0 – FP7.

Floating-Point Status Register: Not Affected. Note that the FMOVEM instruction provides

the only mechanism for moving a ﬂoating- point data item between the ﬂoating-point

unit and memory without performing any data conversions or affecting the condition

code and exception status bits.

Instruction Format:

1514131211109876543210

1111 COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

1 1 dr MODE 0 0 0 REGISTER LIST

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-87

FMOVEM Move Multiple Floating-Point FMOVEM

Data Registers

(MC6888X, MC68040)

Instruction Fields:

Effective Address ﬁeld—(Memory-to-Register) Only control addressing modes or the

postincrement addressing mode can be used as listed in the following table:

Effective Address ﬁeld—(Register-to-Memory) Only control alterable addressing

modes or the predecrement addressing mode can be used as listed in the

following table:

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > — —

(An) + 011 reg. number:An

– (An) — —

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > — —

(An) + — —

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) — —

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) — —

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Floating Point Instructions

5-88 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMOVEM Move Multiple Floating-Point FMOVEM

Data Registers

(MC6888X, MC68040)

dr ﬁeld—Speciﬁes the direction of the transfer.

0 — Move the listed registers from memory to the ﬂoating-point unit.

1 — Move the listed registers from the ﬂoating-point unit to memory.

Mode ﬁeld—Speciﬁes the type of the register list and addressing mode.

00 — Static register list, predecrement addressing mode.

01 — Dynamic register list, predecrement addressing mode.

10 — Static register list, postincrement or control addressing mode.

11 — Dynamic register list, postincrement or control addressing mode.

Static list—contains the register select mask. If a register is to be moved, the corre-

sponding bit in the mask is set as shown below; otherwise it is clear.

Dynamic list—contains the integer data register number, rrr, as listed in the following

table:

The format of the dynamic list mask is the same as for the static list and is contained

in the least significant eight bits of the specified main processor data register.

Programming Note: This instruction provides a very useful feature, dynamic register list

speciﬁcation, that can signiﬁcantly enhance system performance. If the calling

conventions used for procedure calls utilize the dynamic register list feature, the

number of ﬂoating-point data registers saved and restored can be reduced.

To utilize the dynamic register specification feature of the FMOVEM instruction, both

the calling and the called procedures must be written to communicate information

about register usage. When one procedure calls another, a register mask must be

passed to the called procedure to indicate which registers must not be altered upon

return to the calling procedure. The called procedure then saves only those registers

that are modified and are already in use. Several techniques can be used to utilize this

mechanism, and an example follows.

List Type Register List Format

Static, – (An) FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0

Static, (An) + ,

or Control FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7

Dynamic 0 r r r 0000

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-89

FMOVEM Move Multiple Floating-Point FMOVEM

Data Registers

(MC6888X, MC68040)

In this example, a convention is defined by which each called procedure is passed a

word mask in D7 that identifies all floating-point registers in use by the calling proce-

dure. Bits 15 – 8 identify the registers in the order FP0 – FP7, and bits 7 – 0 identify the

registers in the order FP7 – FP0 (the two masks are required due to the different trans-

fer order used by the predecrement and postincrement addressing modes). The code

used by the calling procedure consists of simply moving the mask (which is generated

at compile time) for the floating-point data registers currently in use into D7:

Calling procedure...

The entry code for all other procedures computes two masks. The first mask identifies

the registers in use by the calling procedure that are used by the called procedure (and

therefore saved and restored by the called procedure). The second mask identifies the

registers in use by the calling procedure that are used by the called procedure (and

therefore not saved on entry). The appropriate registers are then stored along with the

two masks:

Called procedure...

If the second procedure calls a third procedure, a register mask is passed to the third

procedure that indicates which registers must not be altered by the third procedure.

This mask identifies any registers in the list from the first procedure that were not saved

by the second procedure, plus any registers used by the second procedure that must

not be altered by the third procedure.

MOVE.W #ACTIVE,D7 Load the list of FP registers that are

in use.

BSR PROC_2

MOVE.W D7,D6 Copy the list of active registers.

AND.W #WILL_USE,D7 Generate the list of doubly-used

registers.

FMOVEM D7, – (A7) Save those registers.

MOVE.W D7, – (A7) Save the register list.

EOR.W D7,D6 Generate the list of not saved active

registers.

MOVE.W D6, – (A7) Save it for later use.

Floating Point Instructions

5-90 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMOVEM Move Multiple Floating-Point FMOVEM

Data Registers

(MC6888X, MC68040)

An example of the calculation of this mask is as follows:

Nested calling sequence...

Upon return from a procedure, the restoration of the necessary registers follows the

same convention, and the register mask generated during the save operation on entry

is used to restore the required floating-point data registers:

Return to caller...

MOVE.W UNSAVED (A7),D7 Load the list of active registers not

saved at entry.

OR.W #WILL_USE,D7 Combine with those active at this time

BSR PROC_3

ADDQ.L #2,A7 Discard the list of registers not saved.

MOVE.B (A7) + ,D7 Get the saved register list (pop word,

use byte).

FMOVEM (A7) + ,D7 Restore the registers.

RTS Return to the calling routine.

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-91

FMOVEM Move Multiple Floating-Point FMOVEM

Control Registers

(MC6888X, MC68040)

Operation: Register List → Destination

Source → Register List

Assembler FMOVEM.L < list > , < ea >

Syntax: FMOVEM.L < ea > , < list >

Attributes: Size = (Long)

Description: Moves one or more 32-bit values into or out of the speciﬁed system control

registers. Any combination of the three system control registers may be speciﬁed. The

registers are always moved in the same order, regardless of the addressing mode

used; the ﬂoating-point control register is moved ﬁrst, followed by the ﬂoating-point

status register, and the ﬂoating-point instruction address register is moved last. If a

registers is the same. The ﬁrst register is transferred between the ﬂoating-point unit and

the speciﬁed address, with successive registers located up through higher addresses.

For the MC68881, this instruction does not cause pending exceptions (other than pro-

tocol violations) to be reported. Furthermore, a write to the floating-point control regis-

ter exception enable byte or the floating-point status register exception status byte

connot generate a new exception, despite the value written.

When more than one register is moved, the memory or memory- alterable addressing

modes can be used as shown in the addressing mode tables. If the addressing mode

is predecrement, the address register is first decremented by the total size of the reg-

ister images to be moved (i.e., four times the number of registers), and then the regis-

ters are transferred starting at the resultant address. For the postincrement addressing

mode, the selected registers are transferred to or from the specified address, and then

the address register is incremented by the total size of the register images transferred.

If a single system control register is selected, the data register direct addressing mode

may be used; if the only register selected is the floating-point instruction address reg-

ister, then the address register direct addressing mode is allowed. Note that if a single

control register instruction.

Floating Point Instructions

5-92 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMOVEM Move Multiple Floating-Point FMOVEM

Control Registers

(MC6888X, MC68040)

Floating-Point Status Register: Changed only if thedestinationlist includes the ﬂoating-

point status register in which case all bits are modiﬁed to reﬂect the value of the source

Instruction Format:

Instruction Fields:

Effective Address ﬁeld—Determines the addressing mode for the operation.

Memory-to-Register—Only control addressing modes or the postincrement

addressing mode can be used as listed in the following table:

*Only if a single ﬂoating-point instruction address register, ﬂoating-point status register, or

ﬂoating-point control register is selected.

**Only if the ﬂoating-point instruction address register is the single register selected.

1514131211109876543210

1111 COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

10dr REGISTER

LIST 0000000000

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An** 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-93

FMOVEM Move Multiple Floating-Point FMOVEM

Control Registers

(MC6888X, MC68040)

addressing mode can be used as listed in the following table:

*Only if a single ﬂoating-point control register is selected.

**Only if the ﬂoating-point instruction address register is the single register selected.

dr ﬁeld—Speciﬁes the direction of the transfer.

0 — Move the listed registers from memory to the ﬂoating-point unit.

1 — Move the listed registers from the ﬂoating-point unit to memory.

corresponding bit in the list is set; otherwise, it is clear. At least one register must

be speciﬁed.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An** 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An # < data > — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) — —

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) — —

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Bit Number Register

12 Floating-Point Control Register

11 Floating-Point Status Register

10 Floating-Point Instruction

Address Register

Floating Point Instructions

5-94 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMUL Floating-Point Multiply FMUL

(MC6888X, MC68040)

Operation: Source x FPn → FPn

Assembler FMUL. < fmt > < ea > ,FPn

Syntax: FMUL.X FPm,FPn

*FrMUL < fmt > < ea > ,FPn

*FrMUL.X FPm,FPn

where r is rounding precision, S or D

*Supported by MC68040 only

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

multiplies that number by the number in the destination ﬂoating-point data register.

Stores the result in the destination ﬂoating-point data register.

FMUL will round the result to the precision selected in the floating-point control register.

FSMUL and FDMUL will round the result to single or double precision, respectively,

regardless of the rounding precision selected in the floating-point control register.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

In Range +

–Multiply + 0.0 – 0.0

– 0.0 + 0.0 + inf – inf

– inf + inf

Zero +

–+ 0.0 – 0.0

– 0.0 + 0.0 + 0.0 – 0.0

– 0.0 + 0.0 NAN2

Infinity +

–+ inf – inf

– inf + inf NAN2+ inf – inf

– inf + inf

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-95

FMUL Floating-Point Multiply FMUL

(MC6888X, MC68040)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set for 0 x infinity; cleared otherwise.

OVFL Refer to exception processing in the

appropriate user’s manual.

UNFL Refer to exception processing in the

appropriate user’s manual.

DZ Cleared

INEX2 Refer to exception processing in the

appropriate user’s manual.

INEX1 If < fmt > is packed, refer to exception

processing in the appropriate user’s manual;

cleared otherwise.

Accrued Exception Byte: Affected as described in exception processing in the appro-

priate user’s manual.

Instruction Format:

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-96 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FMUL Floating-Point Multiply FMUL

(MC6888X, MC68040)

Instruction Fields:

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, speciﬁes the location of the source operand location. Only data

addressing modes can be used as listed in the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)*

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

*This encoding will cause an unimplemented data type exception in the

MC68040 to allow emulation in software.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-97

FMUL Floating-Point Multiply FMUL

(MC6888X, MC68040)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

Opmode ﬁeld—Speciﬁes the instruction and rounding precision.

0100011 FMUL Rounding precision speciﬁed by the ﬂoating-point

control register.

1100011 FSMUL Single-precision rounding speciﬁed.

1100111 FDMUL Double-precision rounding speciﬁed.

Floating Point Instructions

5-98 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FNEG Floating-Point Negate FNEG

(MC6888X, MC68040)

Operation: – (Source) → FPn

Assembler FNEG. < fmt > < ea > ,FPn

Syntax: FNEG.X FPm,FPn

FNEG.X FPn

*FrNEG. < fmt > < ea > ,FPn

*FrNEG.X FPm,FPn

*FrNEG.X FPn

where r is rounding precision, S or D

*Supported by MC68040 only

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and inverts

the sign of the mantissa. Stores the result in the destination ﬂoating-point data register.

FNEG will round the result to the precision selected in the floating-point control register.

FSNEG and FDNEG will round the result to single or double precision, respectively,

regardless of the rounding precision selected in the floating-point control register.

Operation Table:

NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result Negate – 0.0 + 0.0 – inf + inf

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-99

FNEG Floating-Point Negate FNEG

(MC6888X, MC68040)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Cleared

UNFL If source is an extended-precision

denormalized number, refer to exception

processing in the appropriate user’s manual;

cleared otherwise.

DZ Cleared

INEX2 Cleared

INEX1 If < fmt > is packed, refer to exception

processing in the appropriate user’s manual;

cleared otherwise.

Accrued Exception Byte: Affected as described in exception processing in the appro-

priate user’s manual.

Instruction Format:

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-100 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FNEG Floating-Point Negate FNEG

(MC6888X, MC68040)

Instruction Fields:

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, speciﬁes the location of the source operand. Only data addressing modes

can be used as listed in the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)*

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

*This encoding will cause an unimplemented data type exception to allow

emulation in software.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-101

FNEG Floating-Point Negate FNEG

(MC6888X, MC68040)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Opmode ﬁeld—Speciﬁes the instruction and rounding precision.

0011010 FNEG Rounding precision speciﬁed by the ﬂoating-point

control register.

1011010 FSNEG Single-precision rounding speciﬁed.

1011110 FDNEG Double-precision rounding speciﬁed.

Floating Point Instructions

5-102 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FNOP No Operation FNOP

(MC6888X, MC68040)

Operation: None

Assembler

Syntax: FNOP

Attributes: Unsized

Description: This instruction does not perform any explicit operation. However, it is useful

to force synchronization of the ﬂoating- point unit with an integer unit or to force

processing of pending exceptions. For most ﬂoating-point instructions, the integer unit

is allowed to continue with the execution of the next instruction once the ﬂoating-point

unit has any operands needed for an operation, thus supporting concurrent execution

of ﬂoating-point and integer instructions. The FNOP instruction synchronizes the

ﬂoating-point unit and the integer unit by causing the integer unit to wait until all

previous ﬂoating-point instructions have completed. Execution of FNOP also forces

any exceptions pending from the execution of a previous ﬂoating-point instruction to be

processed as a preinstruction exception.

The MC68882 may not wait to begin execution of another floating- point instruction until

it has completed execution of the current instruction. The FNOP instruction synchro-

nizes the coprocessor and microprocessor unit by causing the microprocessor unit to

wait until the current instruction (or both instructions) have completed.

The FNOP instruction also forces the processing of exceptions pending from the exe-

cution of previous instructions. This is also inherent in the way that the floating-point

coprocessor utilizes the M68000 family coprocessor interface. Once the floating-point

coprocessor has received the input operand for an arithmetic instruction, it always

releases the main processor to execute the next instruction (regardless of whether or

not concurrent execution is prevented for the instruction due to tracing) without report-

ing the exception during the execution of that instruction. Then, when the main proces-

sor attempts to initiate the execution of the next floating-point coprocessor instruction,

a preinstruction exception may be reported to initiate exception processing for an

exception that occurred during a previous instruction. By using the FNOP instruction,

the user can force any pending exceptions to be processed without performing any

other operations.

Floating-Point Status Register: Not Affected.

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-103

FNOP No Operation FNOP

(MC6888X, MC68040)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

NOTE

FNOP uses the same opcode as the FBcc.W < label > instruc-

tion, with cc = F (nontrapping false) and < label > = + 2 (which

results in a displacement of 0).

1514131211109876543210

1111COPROCESSOR ID 010000000

0000000000000000

Floating Point Instructions

5-104 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FREM IEEE Remainder FREM

(MC6888X, M68040FPSP)

Operation: IEEE Remainder of (FPn ÷ Source) → FPn

Assembler FREM. < fmt > < ea > ,FPn

Syntax: FREM.X FPm,FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the modulo remainder of the number in the destination ﬂoating-point data

ﬂoating-point data register and stores the sign and seven least signiﬁcant bits of the

quotient in the ﬂoating-point status register quotient byte (the quotient is the result of

FPn ÷ Source). The IEEE remainder function is deﬁned as:

FPn – (Source x N)

where N = INT (FPn ÷ Source) in the round-to-nearest mode.

The FREM function is not defined for a source operand equal to zero or for a destina-

tion operand equal to infinity. Note that this function is not the same as the FMOD

instruction, which uses the round-to-zero mode and thus returns a remainder that is dif-

ferent from the remainder required by the IEEE

Specification for Binary Floating-Point

Arithmetic

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

3. Returns the value of FPn before the operation. However, the result is

processed by the normal instruction termination procedure to round it as

required. Thus, an overﬂow and/or inexact result may occur if the rounding

precision has been changed to a smaller size since the FPn value was loaded.

DESTINATION SOURCE1

+ In Range – + Zero# – + Inﬁnity –

In Range +

–IEEE Remainder NAN2FPn2

Zero +

–+ 0.0

– 0.0 NAN2+ 0.0

– 0.0

Infinity +

–NAN2NAN2NAN†2

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-105

FREM IEEE Remainder FREM

(MC6888X, M68040FPSP)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Loaded with the sign and least significant seven bits of the

qotient (FPn ÷ Source). The sign of the quotient is the

exclusive-OR of the sign bits of the source and destination

operands.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source is zero or the destination is

infinity; cleared otherwise.

OVFL Cleared

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Cleared

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-106 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FREM IEEE Remainder FREM

(MC6888X, M68040FPSP)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-107

FSCALE Scale Exponent FSCALE

(MC6888X, M68040FPSP)

Operation: FPn x INT(2Source) → FPn

Assembler FSCALE. < fmt > < ea > ,FPn

Syntax: FSCALE.X FPm,FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to an integer (if necessary) and adds that integer

to the destination exponent. Stores the result in the destination ﬂoating-point data

much faster than a multiply operation when the source is an integer value.

The floating-point coprocessor assumes that the scale factor is an integer value before

the operation is executed. If not, the value is chopped (i.e., rounded using the round-

to-zero mode) to an integer before it is added to the exponent. When the absolute value

of the source operand is ≥ 214, an overflow or underflow always results.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Returns the value of FPn before the operation. However, the result is

processed by the normal instruction termination procedure to round it as

required. Thus, an overﬂow and/or inexact result may occur if the rounding

precision has been changed to a smaller size since the FPn value was

loaded.

3. Sets the OPERR bit in the ﬂoating-point status register exception byte.

DESTINATION SOURCE1

+ In Range – + Zero – + Infinity –

In Range + – Scale Exponent FPn2NAN3

Zero + – + 0.0 – 0.0 + 0.0 – 0.0 NAN3

Infinity + – + inf – inf + inf – inf NAN3

Floating Point Instructions

5-108 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSCALE Scale Exponent FSCALE

(MC6888X, M68040FPSP)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source operand is ± infinity; cleared

otherwise.

OVFL Refer to overflow in the appropriate user’s

manual.

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Cleared

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-109

FSCALE Scale Exponent FSCALE

(MC6888X, M68040FPSP)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-110 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FScc Set According to Floating-Point Condition FScc

(MC6888X, MC68040)

Operation: If (Condition True)

Then 1s → Destination

Else 0s → Destination

Assembler

Syntax: FScc. < size > < ea >

Attributes: Size = (Byte)

Description: If the speciﬁed ﬂoating-point condition is true, sets the byte integer operand at

the destination to TRUE (all ones); otherwise, sets the byte to FALSE (all zeros). The

conditional speciﬁer cc may select any one of the 32 ﬂoating-point conditional tests as

described in Table 3-23 Floating-Point Conditional Tests.

Floating-Point Status Register:

Condition Codes: Not affected.

Quotient Byte: Not affected.

Exception Byte: BSUN Set if the NAN condition code is set and the

condition selected is an IEEE nonaware test.

SNAN Not Affected.

OPERR Not Affected.

OVFL Not Affected.

UNFL Not Affected.

DZ Not Affected.

INEX2 Not Affected.

INEX1 Not Affected.

Accrued Exception Byte: The IOP bit is set if the BSUN bit is set in the exception

byte. No other bit is affected.

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-111

FScc Set According to Floating-Point Condition FScc

(MC6888X, MC68040)

Instruction Format:

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the addressing mode for the byte integer operand.

Only data alterable addressing modes can be used as listed in the following table:

Conditional Predicate ﬁeld—Speciﬁes one of 32 conditional tests as deﬁned in 3.6.2

Conditional Testing.

NOTE

When a BSUN exception occurs, a preinstruction exception is

taken. If the exception handler returns without modifying the im-

age of the program counter on the stack frame (to point to the

instruction following the FScc), then it must clear the cause of

the exception (by clearing the NAN bit or disabling the BSUN

trap) or the exception occurs again immediately upon return to

the routine that caused the exception.

1514131211109876543210

1111COPROCESSOR

ID 001 EFFECTIVE ADDRESS

MODE REGISTER

0000000000 CONDITIONAL PREDICATE

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) — —

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) — —

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Floating Point Instructions

5-112 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSGLDIV Single-Precision Divide FSGLDIV

(MC6888X, MC68040)

Operation: FPn ÷ Source → FPn

Assembler FSGLDIV. < fmt > < ea > ,FPn

Syntax: FSGLDIV.X FPm,FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and divides

that number into the number in the destination ﬂoating-point data register. Stores the

result in the destination ﬂoating-point data register, rounded to single precision (despite

the current rounding precision). This function is undeﬁned for 0 ÷ 0 and inﬁnity ÷ inﬁnity.

Both the source and destination operands are assumed to be representable in the sin-

gle-precision format. If either operand requires more than 24 bits of mantissa to be

accurately represented, the extraneous mantissa bits are trancated prior to the divi-

sion, hence the accuracy of the result is not guaranteed. Furthermore, the result expo-

nent may exceed the range of single precision, regardless of the rounding precision

selected in the floating-point control register mode control byte. Refer to 3.6.1 Under-

flow, Round, Overflow for more information.

The accuracy of the result is not affected by the number of mantissa bits required to

represent each input operand since the input operands just change to extended preci-

sion. The result mantissa is rounded to single precision, and the result exponent is

rounded to extended precision, despite the rounding precision selected in the floating-

point control register.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the DZ bit in the ﬂoating-point status register exception byte.

3. Sets the OPERR bit in the ﬂoating-point status register exception byte.

DESTINATION SOURCE3,1

+ In Range – + Zero – + Inﬁnity –

In Range +

–Divide

(Single Precision) + inf2 – inf2

– inf2 + inf2+ 0.0 – 0.0

– 0.0 + 0.0

Zero +

–+ 0.0 – 0.0

– 0.0 + 0.0 NAN3+ 0.0 – 0.0

– 0.0 + 0.0

Infinity +

–+ inf – inf

– inf + inf + inf – inf

– inf + inf NAN3

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-113

FSGLDIV Single-Precision Divide FSGLDIV

(MC6888X, MC68040)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set for 0 ÷ 0 or infinity ÷ infinity.

OVFL Refer to overflow in the appropriate user’s

manual.

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Set if the source is zero and the destination is

in range; cleared otherwise.

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to the appropriate

user’s manual for inexact result on decimal

input; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-114 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSGLDIV Single-Precision Divide FSGLDIV

(MC6888X, MC68040)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-115

FSGLMUL Single-Precision Multiply FSGLMUL

(MC6888X, MC68040)

Operation: Source x FPn → FPn

Assembler FSGLMUL. < fmt > < ea > ,FPn

Syntax: FSGLMUL.X FPm,FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

multiplies that number by the number in the destination ﬂoating-point data register.

Stores the result in the destination ﬂoating-point data register, rounded to single

precision (regardless of the current rounding precision).

Both the source and destination operands are assumed to be representable in the sin-

gle-precision format. If either operand requires more than 24 bits of mantissa to be

accurately represented, the extraneous mantissa bits are truncated prior to the multi-

pliction; hence, the accuracy of the result is not guaranteed. Furthermore, the result

exponent may exceed the range of single precision, regardless of the rounding preci-

sion selected in the floating-point control register mode control byte. Refer to 3.6.1

Underflow, Round, Overflow for more information.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

NOTE

The input operand mantissas truncate to single precision before

the multiply operation. The result mantissa rounds to single pre-

cision despite the rounding precision selected in the ﬂoating-

point control register.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

In Range +

–Multiply

(Single Precision) + 0.0 – 0.0

– 0.0 + 0.0 + inf – inf

– inf + inf

Zero +

–+ 0.0 – 0.0

– 0.0 + 0.0 + 0.0 – 0.0

– 0.0 + 0.0 NAN2

Infinity +

–+ inf – inf

– inf + inf NAN + inf – inf

– inf + inf

Floating Point Instructions

5-116 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSGLMUL Single-Precision Multiply FSGLMUL

(MC6888X, MC68040)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if one operand is zero and the other is

infinity; cleared otherwise.

OVFL Refer to overflow in the appropriate user’s

manual.

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-117

FSGLMUL Single-Precision Multiply FSGLMUL

(MC6888X, MC68040)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-118 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSIN Sine FSIN

(MC6888X, M68040FPSP)

Operation: Sine of Source → FPn

Assembler FSIN. < fmt > < ea > ,FPn

Syntax: FSIN.X FPm,FPn

FSIN.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the sine of that number. Stores the result in the destination ﬂoating-point

data register. This function is not deﬁned for source operands of ± inﬁnity. If the source

operand is not in the range of [ – 2π... + 2π], the argument is reduced to within that

range before the sine is calculated. However, large arguments may lose accuracy

during reduction, and very large arguments (greater than approximately 1020) lose all

accuracy. The result is in the range of [ – 1... + 1].

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

Result Sine + 0.0 – 0.0 NAN2

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-119

FSIN Sine FSIN

(MC6888X, M68040FPSP)

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source is ± infinity; cleared

otherwise.

OVFL Cleared

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-120 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSIN Sine FSIN

(MC6888X, M68040FPSP)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, then the input operand is

taken from the speciﬁed ﬂoating-point data register, and the result is written into

the same register. If the single register syntax is used, Motorola assemblers set

the source and destination ﬁelds to the same value.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-121

FSINCOS Simultaneous Sine and Cosine FSINCOS

(MC6888X, M68040FPSP)

Operation: Sine of Source → FPs

Cosine of Source → FPc

Assembler FSINCOS. < fmt > < ea > ,FPc,FPs

Syntax: FSINCOS.X FPm,FPc,FPs

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates both the sine and the cosine of that number. Calculates both functions

simultaneously; thus, this instruction is signiﬁcantly faster than performing separate

FSIN and FCOS instructions. Loads the sine and cosine results into the destination

ﬂoating-point data register. Sets the condition code bits according to the sine result. If

FPs and FPc are speciﬁed to be the same register, the cosine result is ﬁrst loaded into

the register and then is overwritten with the sine result. This function is not deﬁned for

source operands of ± inﬁnity.

If the source operand is not in the range of [ – 2π... + 2π], the argument is reduced to

within that range before the sine and cosine are calculated. However, large arguments

may lose accuracy during reduction, and very large arguments (greater than approxi-

mately 1020) lose all accuracy. The results are in the range of [ – 1... + 1].

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

FPs Sine + 0.0 – 0.0 NAN2

FPc Cosine + 1.0 NAN2

Floating Point Instructions

5-122 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSINCOS Simultaneous Sine and Cosine FSINCOS

(MC6888X, M68040FPSP)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing (for the

sine result).

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source is ± infinity; cleared

otherwise.

OVFL Cleared

UNFL Set if a sine underflow occurs, in which case

the cosine result is 1. Cosine cannot

underflow. Refer to underflow in the

appropriate user’s manual.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-123

FSINCOS Simultaneous Sine and Cosine FSINCOS

(MC6888X, M68040FPSP)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register, FPc ﬁeld—Speciﬁes the destination ﬂoating- point data register,

FPc. The cosine result is stored in this register.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-124 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSINCOS Simultaneous Sine and Cosine FSINCOS

(MC6888X, M68040FPSP)

Destination Register, FPs ﬁeld—Speciﬁes the destination ﬂoating- point data register, FPs.

The sine result is stored in this register. If FPc and FPs specify the same ﬂoating-point

data register, the sine result is stored in the register, and the cosine result is discarded.

If R/M = 0 and the source register field is equal to either of the destination register

fields, the input operand is taken from the specified floating-point data register, and the

appropriate result is written into the same register.

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-125

FSINH Hyperbolic Sine FSINH

(MC6888X, M68040FPSP)

Operation: Hyperbolic Sine of Source → FPn

Assembler FSINH. < fmt > < ea > ,FPn

Syntax: FSINH.X FPm,FPn

FSINH.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the hyperbolic sine of that number. Stores the result in the destination

ﬂoating-point data register.

Operation Table:

NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Refer to overflow in the appropriate user’s

manual.

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result Hyperbolic Sine + 0.0 – 0.0 + inf – inf

Floating Point Instructions

5-126 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSINH Hyperbolic Sine FSINH

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-127

FSINH Hyperbolic Sine FSINH

(MC6888X, M68040FPSP)

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, the input operand is taken

from the speciﬁed ﬂoating-point data register, and the result is written into the

same register. If the single register syntax is used, Motorola assemblers set the

source and destination ﬁelds to the same value.

Floating Point Instructions

5-128 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSQRT Floating-Point Square Root FSQRT

(MC6888X, MC68040)

Operation: Square Root of Source → FPn

Assembler FSQRT. < fmt > < ea > ,FPn

Syntax: FSQRT.X FPm,FPn

FSQRT.X FPn

*FrSQRT. < fmt > < ea > ,FPn

*FrSQRT FPm,FPn

*FrSQRT FPn

where r is rounding precision, S or D

*Supported by MC68040 only

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the square root of that number. Stores the result in the destination ﬂoating-

point data register. This function is not deﬁned for negative operands.

FSQRT will round the result to the precision selected in the floating-point control reg-

ister. FSFSQRT and FDFSQRT will round the result to single or double precision,

respectively, regardless of the rounding precision selected in the floating-point control

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

Result NAN2+ 0.0 – 0.0 + inf NAN2

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-129

FSQRT Floating-Point Square Root FSQRT

(MC6888X, MC68040)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source operand is not zero and is

negative; cleared otherwise.

OVFL Cleared

UNFL Cleared

DZ Cleared

INEX2 Refer to exception processing in the

appropriate user’s manual.

INEX1 If < fmt > is packed, refer to exception

processing in the appropriate user’s manual;

cleared otherwise.

Accrued Exception Byte: Affected as described in exception processing in the appro-

priate user’s manual.

Instruction Format:

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-130 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSQRT Floating-Point Square Root FSQRT

(MC6888X, MC68040)

Instruction Fields:

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, speciﬁes the location of the source operand. Only data addressing modes

can be used as listed in the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)*

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

*This encoding will cause an unimplemented data type exception in the

MC68040 to allow emulation in software.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-131

FSQRT Floating-Point Square Root FSQRT

(MC6888X, MC68040)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, the input operand is taken

from the speciﬁed ﬂoating-point data register, and the result is written into the

same register. If the single register syntax is used, Motorola assemblers set the

source and destination ﬁelds to the same value.

Opmode ﬁeld—Speciﬁes the instruction and rounding precision.

0000100 FSQRT Rounding precision speciﬁed by the ﬂoating-point

control register.

1000001 FSSQRT Single-precision rounding speciﬁed.

1000101 FDSQRT Double-precision rounding speciﬁed.

Floating Point Instructions

5-132 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSUB Floating-Point Subtract FSUB

(MC6888X, MC68040)

Operation: FPn – Source → FPn

Assembler

Syntax: FSUB. < fmt > < ea > ,FPn

FSUB.X FPm,FPn

*FrSUB. < fmt > < ea > ,FPn

*FrSUB.X FPm,FPn

where r is rounding precision, S or D

*Supported by MC68040 only

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

subtracts that number from the number in the destination ﬂoating-point data register.

Stores the result in the destination ﬂoating-point data register.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Returns + 0.0 in rounding modes RN, RZ, and RP; returns – 0.0 in RM.

3. Sets the OPERR bit in the ﬂoating-point status register exception byte.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

In Range +

–Subtract Subtract – inf + inf

Zero +

–Subtract + 0.02+ 0.0

+ 0.0 + 0.02– inf + inf

Infinity +

–+ inf

– inf + inf

– inf NAN2 – inf

– inf NAN2

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-133

FSUB Floating-Point Subtract FSUB

(MC6888X, MC68040)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if both the source and destination are

like-signed infinities; cleared otherwise.

OVFL Refer to exception processing in the

appropriate user’s manual.

UNFL Refer to exception processing in the

appropriate user’s manual.

DZ Cleared

INEX2 Refer to exception processing in the

appropriate user’s manual.

INEX1 If < fmt > is packed, refer to exception

processing in the appropriate user’s manual;

cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-134 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FSUB Floating-Point Subtract FSUB

(MC6888X, MC68040)

Instruction Fields:

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, speciﬁes the location of the source operand. Only data addressing modes

can be used as listed in the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)*

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

*This encoding will cause an unimplemented data type exception in the

MC68040 to allow emulation in software.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-135

FSUB Floating-Point Subtract FSUB

(MC6888X, MC68040)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register.

Opmode ﬁeld—Speciﬁes the instruction and rounding precision.

0101000 FSUB Rounding precision speciﬁed by the ﬂoating- point

control register.

1101000 FSSUB Single-precision rounding speciﬁed.

1101100 FDSUB Double-precision rounding speciﬁed.

Floating Point Instructions

5-136 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FTAN Tangent FTAN

(MC6888X/004SW)

Operation: Tangent of Source → FPn

Assembler FTAN. < fmt > < ea > ,FPn

Syntax: FTAN.X FPm,FPn

FTAN.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the tangent of that number. Stores the result in the destination ﬂoating-point

data register. This function is not deﬁned for source operands of ± inﬁnity. If the source

operand is not in the range of [ – π/2... + π/2], the argument is reduced to within that

range before the tangent is calculated. However, large arguments may lose accuracy

during reduction, and very large arguments (greater than approximately 1020) lose all

accuracy.

Operation Table:

NOTES:

1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

2. Sets the OPERR bit in the ﬂoating-point status register exception byte.

DESTINATION SOURCE1

+ In Range – + Zero – + Inﬁnity –

Result Tangent + 0.0 – 0.0 NAN2

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-137

FTAN Tangent FTAN

(MC6888X/004SW)

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Set if the source is ± infinity; cleared

otherwise.

OVFL Refer to overflow in the appropriate user’s

manual.

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Floating Point Instructions

5-138 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FTAN Tangent FTAN

(MC6888X/004SW)

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, the input operand is taken

from the speciﬁed ﬂoating-point data register, and the result is written into the

same register. If the single register syntax is used, Motorola assemblers set the

source and destination ﬁelds to the same value.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-139

FTANH Hyperbolic Tangent FTANH

(MC6888X, M68040FPSP)

Operation: Hyperbolic Tangent of Source → FPn

Assembler FTANH. < fmt > < ea > ,FPn

Syntax: FTANH.X FPm,FPn

FTANH.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates the hyperbolic tangent of that number. Stores the result in the destination

ﬂoating-point data register.

Operation Table:

NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Cleared

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result Hyperbolic Tangent + 0.0 – 0.0 + 1.0 – 1.0

Floating Point Instructions

5-140 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FTANH Hyperbolic Tangent FTANH

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-141

FTANH Hyperbolic Tangent FTANH

(MC6888X, M68040FPSP)

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, the input operand is taken

from the speciﬁed ﬂoating-point data register, and the result is written into the

same register. If the single register syntax is used, Motorola assemblers set the

source and destination ﬁelds to the same value.

Floating Point Instructions

5-142 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FTENTOX 10xFTENTOX

(MC6888X, M68040FPSP)

Operation: 10Source → FPn

Assembler FTENTOX. < fmt > < ea > ,FPn

Syntax: FTENTOX.X FPm,FPn

FTENTOX.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates 10 to the power of that number. Stores the result in the destination ﬂoating-

point data register.

Operation Table:

NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Refer to overflow in the appropriate user’s

manual.

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to the appropriate

user’s manual inexact result on decimal

input; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result 10x+ 1.0 + inf + 0.0

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-143

FTENTOX 10xFTENTOX

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-144 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FTENTOX 10xFTENTOX

(MC6888X, M68040FPSP)

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, the input operand is taken

from the speciﬁed ﬂoating-point data register, and the result is written into the

same register. If the single register syntax is used, Motorola assemblers set the

source and destination ﬁelds to the same value.

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-145

FTRAPcc Trap on Floating-Point Condition FTRAPcc

(MC6888X, MC68040)

Operation: If Condition True

Then TRAP

Assembler FTRAPcc

Syntax: FTRAPcc.W # < data >

FTRAPcc.L # < data >

Attributes: Size = (Word, Long)

Description: If the selected condition is true, the processor initiates exception processing.

A vector number is generated to reference the TRAPcc exception vector. The stacked

program counter points to the next instruction. If the selected condition is not true, there

is no operation performed and execution continues with the next instruction in

sequence. The immediate data operand is placed in the word(s) following the

conditional predicate word and is available for user deﬁnition for use within the trap

handler.

The conditional specifier cc selects one of the 32 conditional tests defined in 3.6.2

Conditional Testing.

Floating-Point Status Register:

Condition Codes: Not affected.

Quotient Byte: Not affected.

Exception Byte: BSUN Set if the NAN condition code is set and the

condition selected is an IEEE nonaware test.

SNAN Not Affected.

OPERR Not Affected.

OVFL Not Affected.

UNFL Not Affected.

DZ Not Affected.

INEX2 Not Affected.

INEX1 Not Affected.

Accrued Exception Byte: The IOP bit is set if the BSUN bit is set in the exception

byte; no other bit is affected.

Floating Point Instructions

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FTRAPcc Trap on Floating-Point Condition FTRAPcc

(MC6888X, MC68040)

Instruction Format:

Instruction Fields:

Mode ﬁeld—Speciﬁes the form of the instruction.

010 — The instruction is followed by a word operand.

011 —The instruction is followed by a long-word operand.

100 — The instruction has no operand.

Conditional Predicate ﬁeld—Speciﬁes one of 32 conditional tests as described in 3.6.2

Conditional Testing.

Operand ﬁeld—Contains an optional word or long-word operand that is user deﬁned.

NOTE

When a BSUN exception occurs, a preinstruction exception is

taken by the main processor. If the exception handler returns

without modifying the image of the program counter on the stack

frame (to point to the instruction following the FTRAPcc), it must

clear the cause of the exception (by clearing the NAN bit or dis-

abling the BSUN trap), or the exception occurs again immediate-

ly upon return to the routine that caused the exception.

1514131211109876543210

1111COPROCESSOR

ID 001111 MODE

0000000000 CONDITIONAL PREDICATE

16-BIT OPERAND OR MOST SIGNIFICANT WORD OF 32-BIT OPERAND (IFNEEDED)

LEAST SIGNIFICANT WORD OR 32-BIT OPERAND (IF NEEDED)

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-147

FTST Test Floating-Point Operand FTST

(MC6888X, MC68040)

Operation: Condition Codes for Operand → FPCC

Assembler FTST. < fmt > < ea >

Syntax: FTST.X FPm

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and sets the

condition code bits according to the data type of the result.

Operation Table: The contents of this table differfromtheother operation tables. A letter in

an entry of this table indicates that the designated condition code bit is always set by

the FTST operation. All unspeciﬁed condition code bits are cleared during the

operation.

NOTE: If the source operand is a NAN, set the NAN condition code bit. If the source

operand is an SNAN, set the SNAN bit in the ﬂoating-point status register

exception byte

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Cleared

UNFL Cleared

DZ Cleared

INEX2 Cleared

INEX1 If < fmt > is packed, refer to exception

processing in the appropriate user’s manual;

cleared otherwise.

Accrued Exception Byte: Affected as described in exception processing in the appro-

priate user’s manual.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result none N Z NZ I NI

Floating Point Instructions

5-148 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FTST Test Floating-Point Operand FTST

(MC6888X, MC68040)

Instruction Format:

Instruction Fields:

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, speciﬁes the location of the source operand. Only data addressing modes

can be used as listed in the following table:

*Only if < fmt > is byte, word, long, or single.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-149

FTST Test Floating-Point Operand FTST

(MC6888X, MC68040)

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)*

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

*This encoding will cause an unimplemented data type exception in the

MC68040 to allow emulation in software.

Destination Register ﬁeld—Since the ﬂoating-point unit uses a common command

word format for all of the arithmetic instructions (including FTST), this ﬁeld is

treated in the same manner for FTST as for the other arithmetic instructions, even

though the destination register is not modiﬁed. This ﬁeld should be set to zero to

maintain compatibility with future devices; however, the ﬂoating-point unit does

not signal an illegal instruction trap if it is not zero.

Floating Point Instructions

5-150 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FTWOTOX 2xFTWOTOX

(MC6888X, M68040FPSP)

Operation: 2Source → FPn

Assembler FTWOTOX. < fmt > < ea > ,FPn

Syntax: FTWOTOX.X FPm,FPn

FTWOTOX.X FPn

Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)

Description: Converts the source operand to extended precision (if necessary) and

calculates two to the power of that number. Stores the result in the destination ﬂoating-

point data register.

Operation Table:

NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.

Floating-Point Status Register:

Condition Codes: Affected as described in 3.6.2 Conditional Testing.

Quotient Byte: Not affected.

Exception Byte: BSUN Cleared

SNAN Refer to 1.6.5 Not-A-Numbers.

OPERR Cleared

OVFL Refer to overflow in the appropriate user’s

manual.

UNFL Refer to underflow in the appropriate user’s

manual.

DZ Cleared

INEX2 Refer to inexact result in the appropriate

user’s manual.

INEX1 If < fmt > is packed, refer to inexact result on

decimal input in the appropriate user’s

manual; cleared otherwise.

Accrued Exception Byte: Affected as described in IEEE exception and trap compati-

bility in the appropriate user’s manual.

DESTINATION SOURCE

+ In Range – + Zero – + Inﬁnity –

Result 2x+ 1.0 + inf + 0.0

Floating Point Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-151

FTWOTOX 2xFTWOTOX

(MC6888X, M68040FPSP)

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Speciﬁes which coprocessor in the system is to execute this

instruction. Motorola assemblers default to ID = 1 for the ﬂoating-point

coprocessor.

Effective Address ﬁeld—Determines the addressing mode for external operands.

If R/M = 0, this ﬁeld is unused and should be all zeros.

If R/M = 1, this ﬁeld is encoded with an M68000 family addressing mode as listed in

the following table:

*Only if < fmt > is byte, word, long, or single.

1514131211109876543210

1111COPROCESSOR

ID 000 EFFECTIVE ADDRESS

MODE REGISTER

0 R/M 0 SOURCE

SPECIFIER DESTINATION

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An # < data > 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Floating Point Instructions

5-152 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FTWOTOX 2xFTWOTOX

(MC6888X, M68040FPSP)

R/M ﬁeld—Speciﬁes the source operand address mode.

0 — The operation is register to register.

1 — The operation is < ea > to register.

Source Speciﬁer ﬁeld—Speciﬁes the source register or data format.

If R/M = 0, speciﬁes the source ﬂoating-point data register.

If R/M = 1, speciﬁes the source data format:

000 — Long-Word Integer (L)

001 — Single-Precision Real (S)

010 — Extended-Precision Real (X)

011 —Packed-Decimal Real (P)

100 — Word Integer (W)

101 — Double-Precision Real (D)

110 —Byte Integer (B)

Destination Register ﬁeld—Speciﬁes the destination ﬂoating- point data register. If R/

M = 0 and the source and destination ﬁelds are equal, the input operand is taken

from the speciﬁed ﬂoating-point data register, and the result is written into the

same register. If the single register syntax is used, Motorola assemblers set the

source and destination ﬁelds to the same value.