Integer Instructions

4-2

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

MOTOROLA

ABCD

Add Decimal with Extend

ABCD

(M68000 Family)

Operation:

Source10 + Destination10 + X

→

Destination

Assembler

ABCD Dy,Dx

Syntax:

ABCD – (Ay), – (Ax)

Attributes:

Size = (Byte)

Description:

Adds the source operand to the destination operand along with the extend bit,

and stores the result in the destination location. The addition is performed using binary-

coded decimal arithmetic. The operands, which are packed binary-coded decimal

numbers, can be addressed in two different ways:

1. Data Register to Data Register: The operands are contained in the data regis-

ters specified in the instruction.

2. Memory to Memory: The operands are addressed with the predecrement ad-

dressing mode using the address registers specified in the instruction.

This operation is a byte operation only.

Condition Codes:

X — Set the same as the carry bit.

N — Undeﬁned.

Z — Cleared if the result is nonzero; unchanged otherwise.

V — Undeﬁned.

C — Set if a decimal carry was generated; cleared otherwise.

NOTE

Normally, the Z condition code bit is set via programming before

the start of an operation. This allows successful tests for zero

results upon completion of multiple-precision operations.

XNZVC

Integer Instructions

MOTOROLA

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

4-3

ABCD

Add Decimal with Extend

ABCD

(M68000 Family)

Instruction Format:

Instruction Fields:

If R/M = 0, speciﬁes a data register.

If R/M = 1, speciﬁes an address register for the predecrement addressing mode.

R/M ﬁeld—Speciﬁes the operand addressing mode.

0 — The operation is data register to data register.

1 — The operation is memory to memory.

If R/M = 0, speciﬁes a data register.

If R/M = 1, speciﬁes an address register for the predecrement addressing mode.

1514131211109876543210

1100 REGISTER Rx 10000R/MREGISTER Ry

Integer Instructions

4-4

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

MOTOROLA

ADD

Add

ADD

(M68000 Family)

Operation:

Source + Destination

→

Destination

Assembler

ADD < ea > ,Dn

Syntax:

ADD Dn, < ea >

Attributes:

Size = (Byte, Word, Long)

Description:

Adds the source operand to the destination operand using binary addition and

stores the result in the destination location. The size of the operation may be speciﬁed

as byte, word, or long. The mode of the instruction indicates which operand is the

source and which is the destination, as well as the operand size.

Condition Codes:

X — Set the same as the carry bit.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if an overﬂow is generated; cleared otherwise.

C — Set if a carry is generated; cleared otherwise.

Instruction Format:

XNZVC

∗∗∗∗∗

1514131211109876543210

1101 REGISTER OPMODE

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

MOTOROLA

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

4-5

ADD

Add

ADD

(M68000 Family)

Instruction Fields:

Opmode ﬁeld

Effective Address ﬁeld—Determines addressing mode.

a. If the location specified is a source operand, all addressing modes can be used

as listed in the following tables:

*Word and long only

**Can be used with CPU32.

Byte Word Long Operation

000 001 010 < ea > + Dn

→

100 101 110 Dn + < ea >

→

< ea >

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An* 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)† 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-6

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

MOTOROLA

ADD

Add

ADD

(M68000 Family)

b. If the location specified is a destination operand, only memory alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32

NOTE

The Dn mode is used when the destination is a data register; the

destination < ea > mode is invalid for a data register.

ADDA is used when the destination is an address register. ADDI

and ADDQ are used when the source is immediate data. Most

assemblers automatically make this distinction.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

4-7

ADDA

Add Address

ADDA

(M68000 Family)

Operation:

Source + Destination

→

Destination

Assembler

Syntax:

ADDA < ea > , An

Attributes:

Size = (Word, Long)

Description:

Adds the source operand to the destination address register and stores the

result in the address register. The size of the operation may be speciﬁed as word or

long. The entire destination address register is used regardless of the operation size.

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

destination.

Opmode ﬁeld—Speciﬁes the size of the operation.

011—Word operation; the source operand is sign-extended to a long operand and

the operation is performed on the address register using all 32 bits.

111— Long operation.

1514131211109876543210

1101 REGISTER OPMODE

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

4-8

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

MOTOROLA

ADDA

Add Address

ADDA

(M68000 Family)

Effective Address ﬁeld—Speciﬁes the source operand. All addressing modes can be

used as listed in the following tables:

*Can be used with CPU32

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

4-9

ADDI

Add Immediate

ADDI

(M68000 Family)

Operation:

Immediate Data + Destination → Destination

Assembler

Syntax: ADDI # < data > , < ea >

Attributes: Size = (Byte, Word, Long)

Description: Adds the immediate data to the destination operand and stores the result in

the destination location. The size of the operation may be speciﬁed as byte, word, or

long. The size of the immediate data matches the operation size.

Condition Codes:

X — Set the same as the carry bit.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if an overﬂow is generated; cleared otherwise.

C — Set if a carry is generated; cleared otherwise.

Instruction Format:

XNZVC

*****

1514131211109876543210

00000110 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

16-BIT WORD DATA 8-BIT BYTE DATA

32-BIT LONG DATA

Integer Instructions

4-10 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

ADDI Add Immediate ADDI

(M68000 Family)

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

Effective Address ﬁeld—Speciﬁes the destination operand. Only data alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32

Immediate ﬁeld—Data immediately following the instruction.

If size = 00, the data is the low-order byte of the immediate word.

If size = 01, the data is the entire immediate word.

If size = 10, the data is the next two immediate words.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-11

ADDQ Add Quick ADDQ

(M68000 Family)

Operation: Immediate Data + Destination → Destination

Assembler

Syntax: ADDQ # < data > , < ea >

Attributes: Size = (Byte, Word, Long)

Description: Adds an immediate value of one to eight to the operand at the destination

location. The size of the operation may be speciﬁed as byte, word, or long. Word and

long operations are also allowed on the address registers. When adding to address

registers, the condition codes are not altered, and the entire destination address

Condition Codes:

X — Set the same as the carry bit.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if an overﬂow occurs; cleared otherwise.

C — Set if a carry occurs; cleared otherwise.

The condition codes are not affected when the destination is an address register.

Instruction Format:

XNZVC

*****

1514131211109876543210

0101 DATA 0 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

4-12 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

ADDQ Add Quick ADDQ

(M68000 Family)

Instruction Fields:

Data ﬁeld—Three bits of immediate data representing eight values (0 – 7), with the

immediate value zero representing a value of eight.

Size ﬁeld—Speciﬁes the size of the operation.

00— Byte operation

01— Word operation

10— Long operation

Effective Address ﬁeld—Speciﬁes the destination location. Only alterable addressing

modes can be used as listed in the following tables:

*Word and long only.

**Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn** 110 reg. number:An (bd,PC,Xn)† — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-13

ADDX Add Extended ADDX

(M68000 Family)

Operation: Source + Destination + X → Destination

Assembler ADDX Dy,Dx

Syntax: ADDX – (Ay), – (Ax)

Attributes: Size = (Byte, Word, Long)

Description: Adds the source operand and the extend bit to the destination operand and

stores the result in the destination location. The operands can be addressed in two

different ways:

1. Data register to data register—The data registers specified in the instruction

contain the operands.

2. Memory to memory—The address registers specified in the instruction address

the operands using the predecrement addressing mode.

The size of the operation can be specified as byte, word, or long.

Condition Codes:

X — Set the same as the carry bit.

N — Set if the result is negative; cleared otherwise.

Z — Cleared if the result is nonzero; unchanged otherwise.

V — Set if an overﬂow occurs; cleared otherwise.

C — Set if a carry is generated; cleared otherwise.

NOTE

Normally, the Z condition code bit is set via programming before

the start of an operation. This allows successful tests for zero

results upon completion of multiple-precision operations.

XNZVC

*****

Integer Instructions

4-14 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

ADDX Add Extended ADDX

(M68000 Family)

Instruction Format:

Instruction Fields:

If R/M = 0, speciﬁes a data register.

If R/M = 1, speciﬁes an address register for the predecrement addressing mode.

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

R/M ﬁeld—Speciﬁes the operand address mode.

0 — The operation is data register to data register.

1 — The operation is memory to memory.

If R/M = 0, speciﬁes a data register.

If R/M = 1, speciﬁes an address register for the predecrement addressing mode.

1514131211109876543210

1101 REGISTER Rx 1 SIZE 0 0 R/M REGISTER Ry

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-15

AND AND Logical AND

(M68000 Family)

Operation: Source L Destination → Destination

Assembler AND < ea > ,Dn

Syntax: AND Dn, < ea >

Attributes: Size = (Byte, Word, Long)

Description: Performs an AND operation of the source operand with the destination

operand and stores the result in the destination location. The size of the operation can

be speciﬁed as byte, word, or long. The contents of an address register may not be

used as an operand.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the result is set; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

Instruction Fields:

Opmode ﬁeld

XNZVC

—

1514131211109876543210

1100 REGISTER OPMODE

EFFECTIVE ADDRESS

MODE REGISTER

Byte Word Long Operation

000 001 010 < ea > Λ Dn → Dn

100 101 110 Dn Λ < ea > → < ea >

Integer Instructions

4-16 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

AND AND Logical AND

(M68000 Family)

Effective Address ﬁeld—Determines addressing mode.

a. If the location specified is a source operand, only data addressing modes can be

used as listed in the following tables:

*Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-17

AND AND Logical AND

(M68000 Family)

b. If the location specified is a destination operand, only memory alterable address-

ing modes can be used as listed in the following tables:

*Can be used with CPU32.

NOTE

The Dn mode is used when the destination is a data register; the

destination < ea > mode is invalid for a data register.

Most assemblers use ANDI when the source is immediate data.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-18 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

ANDI AND Immediate ANDI

(M68000 Family)

Operation: Immediate Data Λ Destination → Destination

Assembler

Syntax: ANDI # < data > , < ea >

Attributes: Size = (Byte, Word, Long)

Description: Performs an AND operation of the immediate data with the destination

operand and stores the result in the destination location. The size of the operation can

be speciﬁed as byte, word, or long. The size of the immediate data matches the

operation size.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the result is set; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—

1514131211109876543210

00000010 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

16-BIT WORD DATA 8-BIT BYTE DATA

32-BIT LONG DATA

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-19

ANDI AND Immediate ANDI

(M68000 Family)

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

Effective Address ﬁeld—Speciﬁes the destination operand. Only data alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32

Immediate ﬁeld—Data immediately following the instruction.

If size = 00, the data is the low-order byte of the immediate word.

If size = 01, the data is the entire immediate word.

If size = 10, the data is the next two immediate words.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-20 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

ANDI ANDI

to CCR CCR AND Immediate to CCR

(M68000 Family)

Operation: Source Λ CCR → CCR

Assembler

Syntax: ANDI # < data > ,CCR

Attributes: Size = (Byte)

Description: Performs an AND operation of the immediate operand with the condition

codes and stores the result in the low-order byte of the status register.

Condition Codes:

X — Cleared if bit 4 of immediate operand is zero; unchanged otherwise.

N — Cleared if bit 3 of immediate operand is zero; unchanged otherwise.

Z — Cleared if bit 2 of immediate operand is zero; unchanged otherwise.

V — Cleared if bit 1 of immediate operand is zero; unchanged otherwise.

C — Cleared if bit 0 of immediate operand is zero; unchanged otherwise.

Instruction Format:

XNZVC

*****

1514131211109876543210

0000001000111100

00000000 8-BIT BYTE DATA

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-21

ASL, ASR Arithmetic Shift ASL, ASR

(M68000 Family)

Operation: Destination Shifted By Count → Destination

Assembler ASd Dx,Dy

Syntax: ASd # < data > ,Dy

ASd < ea >

where d is direction, L or R

Attributes: Size = (Byte, Word, Long)

Description: Arithmetically shifts the bits of the operand in the direction (L or R) speciﬁed.

The carry bit receives the last bit shifted out of the operand. The shift count for the

shifting of a register may be speciﬁed in two different ways:

1. Immediate—The shift count is specified in the instruction (shift range, 1 – 8).

2. Register—The shift count is the value in the data register specified in instruction

modulo 64.

The size of the operation can be specified as byte, word, or long. An operand in mem-

ory can be shifted one bit only, and the operand size is restricted to a word.

For ASL, the operand is shifted left; the number of positions shifted is the shift count.

Bits shifted out of the high-order bit go to both the carry and the extend bits; zeros are

shifted into the low-order bit. The overflow bit indicates if any sign changes occur dur-

ing the shift.

C OPERAND O

ASL:

Integer Instructions

4-22 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

ASL, ASR Arithmetic Shift ASL, ASR

(M68000 Family)

For ASR, the operand is shifted right; the number of positions shifted is the shift count.

Bits shifted out of the low-order bit go to both the carry and the extend bits; the sign bit

(MSB) is shifted into the high-order bit.

Condition Codes:

X — Set according to the last bit shifted out of the operand; unaffected for a shift

count of zero.

N — Set if the most signiﬁcant bit of the result is set; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if the most signiﬁcant bit is changed at any time during the shift operation;

cleared otherwise.

C — Set according to the last bit shifted out of the operand; cleared for a shift count

of zero.

Instruction Format:

Instruction Fields:

Count/Register ﬁeld—Speciﬁes shift count or register that contains the shift count:

If i/r = 0, this ﬁeld contains the shift count. The values 1 – 7 represent counts of 1 –

7; a value of zero represents a count of eight.

If i/r = 1, this ﬁeld speciﬁes the data register that contains the shift count (modulo 64).

XNZVC

*****

1514131211109876543210

1110

COUNT?

dr SIZE i/r 0 0 REGISTER

OPERAND C

ASR:

MSB

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-23

ASL, ASR Arithmetic Shift ASL, ASR

(M68000 Family)

dr ﬁeld—Speciﬁes the direction of the shift.

0 — Shift right

1 — Shift left

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

i/r ﬁeld

If i/r = 0, speciﬁes immediate shift count.

If i/r = 1, speciﬁes register shift count.

Instruction Format:

MEMORY SHIFTS

Instruction Fields:

dr ﬁeld—Speciﬁes the direction of the shift.

0 — Shift right

1 — Shift left

1514131211109876543210

1110000dr11

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

4-24 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

ASL, ASR Arithmetic Shift ASL, ASR

(M68000 Family)

Effective Address ﬁeld—Speciﬁes the operand to be shifted. Only memory alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-25

Bcc Branch Conditionally Bcc

(M68000 Family)

Operation: If Condition True

Then PC + d

→ PC

Assembler

Syntax: Bcc < label >

Attributes: Size = (Byte, Word, Long*)

*(MC68020, MC68030, and MC68040 only)

Description: If the speciﬁed condition is true, program execution continues at location (PC)

+ displacement. The program counter contains the address of the instruction word for

the Bcc instruction plus two. The displacement is a twos-complement integer that

represents the relative distance in bytes from the current program counter to the

destination program counter. If the 8-bit displacement ﬁeld in the instruction word is

zero, a 16-bit displacement (the word immediately following the instruction) is used. If

the 8-bit displacement ﬁeld in the instruction word is all ones ($FF), the 32-bit

displacement (long word immediately following the instruction) is used. Condition code

cc speciﬁes one of the following conditional tests (refer to Table 3-19 for more

information on these conditional tests):

Condition Codes:

Not affected.

Mnemonic Condition Mnemonic Condition

CC(HI) Carry Clear LS Low or Same

CS(LO) Carry Set LT Less Than

EQ Equal MI Minus

GE Greater or Equal NE Not Equal

GT Greater Than PL Plus

HI High VC Overflow Clear

LE Less or Equal VS Overflow Set

Integer Instructions

4-26 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

Bcc Branch Conditionally Bcc

(M68000 Family)

Instruction Format:

Instruction Fields:

Condition ﬁeld—The binary code for one of the conditions listed in the table.

8-Bit Displacement ﬁeld—Twos complement integer specifying the number of bytes

between the branch instruction and the next instruction to be executed if the

condition is met.

16-Bit Displacement ﬁeld—Used for the displacement when the 8-bit displacement

ﬁeld contains $00.

32-Bit Displacement ﬁeld—Used for the displacement when the 8-bit displacement

ﬁeld contains $FF.

NOTE

A branch to the immediately following instruction automatically

uses the 16-bit displacement format because the 8-bit

displacement ﬁeld contains $00 (zero offset).

1514131211109876543210

0110 CONDITION 8-BIT DISPLACEMENT

16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00

32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-27

BCHG Test a Bit and Change BCHG

(M68000 Family)

Operation: TEST ( < number > of Destination) → Z;

TEST ( < number > of Destination) → < bit number > of Destination

Assembler BCHG Dn, < ea >

Syntax: BCHG # < data > , < ea >

Attributes: Size = (Byte, Long)

Description: Tests a bit in the destination operand and sets the Z condition code

appropriately, then inverts the speciﬁed bit in the destination. When the destination is

a data register, any of the 32 bits can be speciﬁed by the modulo 32-bit number. When

the destination is a memory location, the operation is a byte operation, and the bit

number is modulo 8. In all cases, bit zero refers to the least signiﬁcant bit. The bit

number for this operation may be speciﬁed in either of two ways:

1. Immediate—The bit number is specified in a second word of the instruction.

2. Register—The specified data register contains the bit number.

Condition Codes:

X — Not affected.

N — Not affected.

Z — Set if the bit tested is zero; cleared otherwise.

V — Not affected.

C — Not affected.

XNZVC

——

Integer Instructions

4-28 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BCHG Test a Bit and Change BCHG

(M68000 Family)

Instruction Format:

BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the destination location. Only data alterable

addressing modes can be used as listed in the following tables:

*Long only; all others are byte only.

**Can be used with CPU32.

1514131211109876543210

0000 REGISTER 1 0 1

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)† — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-29

BCHG Test a Bit and Change BCHG

(M68000 Family)

Instruction Format:

BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the destination location. Only data alterable

addressing modes can be used as listed in the following tables:

*Long only; all others are byte only.

**Can be used with CPU32.

Bit Number ﬁeld—Speciﬁes the bit number.

1514131211109876543210

0000100001

EFFECTIVE ADDRESS

MODE REGISTER

00000000 BIT NUMBER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)† — (bd,An,Xn)**

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — ([bd,An,Xn],od)

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — ([bd,An],Xn,od)

Integer Instructions

4-30 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BCLR Test a Bit and Clear BCLR

(M68000 Family)

Operation: TEST ( < bit number > of Destination) → Z; 0 → < bit number > of Des-

tination

Assembler BCLR Dn, < ea >

Syntax: BCLR # < data > , < ea >

Attributes: Size = (Byte, Long)

Description: Tests a bit in the destination operand and sets the Z condition code

appropriately, then clears the speciﬁed bit in the destination. When a data register is

the destination, any of the 32 bits can be speciﬁed by a modulo 32-bit number. When

a memory location is the destination, the operation is a byte operation, and the bit

number is modulo 8. In all cases, bit zero refers to the least signiﬁcant bit. The bit

number for this operation can be speciﬁed in either of two ways:

1. Immediate—The bit number is specified in a second word of the instruction.

2. Register—The specified data register contains the bit number.

Condition Codes:

X — Not affected.

N — Not affected.

Z — Set if the bit tested is zero; cleared otherwise.

V — Not affected.

C — Not affected.

XNZVC

——

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-31

BCLR Test a Bit and Clear BCLR

(M68000 Family)

Instruction Format:

BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the destination location. Only data alterable

addressing modes can be used as listed in the following tables:

*Long only; all others are byte only.

**Can be used with CPU32.

1514131211109876543210

0000 REGISTER 1 1 0

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)† — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-32 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BCLR Test a Bit and Clear BCLR

(M68000 Family)

Instruction Format:

BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the destination location. Only data alterable

addressing modes can be used as listed in the following tables:

*Long only; all others are byte only.

**Can be used with CPU32.

Bit Number ﬁeld—Speciﬁes the bit number.

1514131211109876543210

0000100010

EFFECTIVE ADDRESS

MODE REGISTER

00000000 BIT NUMBER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)† — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-33

BFCHG Test Bit Field and Change BFCHG

(MC68020, MC68030, MC68040)

Operation: TEST ( < bit ﬁeld > of Destination) → < bit ﬁeld > of Destination

Assembler

Syntax: BFCHG < ea > {offset:width}

Attributes: Unsized

Description: Sets the condition codes according to the value in a bit ﬁeld at the speciﬁed

effective address, then complements the ﬁeld.

A field offset and a field width select the field. The field offset specifies the starting bit

of the field. The field width determines the number of bits in the field.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the ﬁeld is set; cleared otherwise.

Z — Set if all bits of the ﬁeld are zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

NOTE

For the MC68020, MC68030, and MC68040, all bit ﬁeld

instructions access only those bytes in memory that contain

some portion of the bit ﬁeld. The possible accesses are byte,

word, 3-byte, long word, and long word with byte (for a 5-byte

access).

XNZVC

—

1514131211109876543210

1110101011

EFFECTIVE ADDRESS

MODE REGISTER

0000Do OFFSET Dw WIDTH

Integer Instructions

4-34 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BFCHG Test Bit Field and Change BFCHG

(MC68020, MC68030, MC68040)

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the base location for the bit ﬁeld. Only data register

direct or control alterable addressing modes can be used as listed in the following

table:

Do ﬁeld—Determines how the ﬁeld offset is speciﬁed.

0 — The offset ﬁeld contains the bit ﬁeld offset.

1 — Bits 8 – 6 of the extension word specify a data register that contains the offset;

bits 10 – 9 are zero.

Offset ﬁeld—Speciﬁes the ﬁeld offset, depending on Do.

If Do = 0, the offset ﬁeld is an immediate operand; the operand value is in the range

0 – 31.

If Do = 1, the offset ﬁeld speciﬁes a data register that contains the offset. The value

is in the range of – 2

to 2

– 1.

Dw ﬁeld—Determines how the ﬁeld width is speciﬁed.

0 — The width ﬁeld contains the bit ﬁeld width.

1 — Bits 2 – 0 of the extension word specify a data register that contains the width;

bits 3 – 4 are zero.

Width ﬁeld—Speciﬁes the ﬁeld width, depending on Dw.

If Dw = 0, the width ﬁeld is an immediate operand; an operand value in the range 1

– 31 speciﬁes a ﬁeld width of 1 – 31, and a value of zero speciﬁes a width of 32.

If Dw = 1, the width ﬁeld speciﬁes a data register that contains the width. The value

is modulo 32; values of 1 – 31 specify ﬁeld widths of 1 – 31, and a value of zero

speciﬁes a width of 32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-35

BFCLR Test Bit Field and Clear BFCLR

(MC68020, MC68030, MC68040)

Operation: 0 → < bit ﬁeld > of Destination

Assembler

Syntax: BFCLR < ea > {offset:width}

Attributes: Unsized

Description: Sets condition codes according to the value in a bit ﬁeld at the speciﬁed

effective address and clears the ﬁeld.

The field offset and field width select the field. The field offset specifies the starting bit

of the field. The field width determines the number of bits in the field.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the ﬁeld is set; cleared otherwise.

Z — Set if all bits of the ﬁeld are zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—

1514131211109876543210

1110110011

EFFECTIVE ADDRESS

MODE REGISTER

0000Do OFFSET Dw WIDTH

Integer Instructions

4-36 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BFCLR Test Bit Field and Clear BFCLR

(MC68020, MC68030, MC68040)

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the base location for the bit ﬁeld. Only data register

direct or control alterable addressing modes can be used as listed in the following

table:

Do ﬁeld—Determines how the ﬁeld offset is speciﬁed.

0 — The offset ﬁeld contains the bit ﬁeld offset.

1 — Bits 8 – 6 of the extension word specify a data register that contains the offset;

bits 10 – 9 are zero.

Offset ﬁeld—Speciﬁes the ﬁeld offset, depending on Do.

If Do = 0, the offset ﬁeld is an immediate operand; the operand value is in the range

of 0 – 31.

If Do = 1, the offset ﬁeld speciﬁes a data register that contains the offset. The value

is in the range of – 2

to 2

– 1.

Dw ﬁeld—Determines how the ﬁeld width is speciﬁed.

0 — The width ﬁeld contains the bit ﬁeld width.

1 — Bits 2 – 0 of the extension word specify a data register that contains the width;

bits 3 – 4 are zero.

Width ﬁeld—Speciﬁes the ﬁeld width, depending on Dw.

If Dw = 0, the width ﬁeld is an immediate operand; operand values in the range of 1

– 31 specify a ﬁeld width of 1 – 31, and a value of zero speciﬁes a width of 32.

If Dw = 1, the width ﬁeld speciﬁes a data register that contains the width. The value

is modulo 32; values of 1 – 31 specify ﬁeld widths of 1 – 31, and a value of zero

speciﬁes a width of 32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-37

BFEXTS Extract Bit Field Signed BFEXTS

(MC68020, MC68030, MC68040)

Operation: < bit ﬁeld > of Source → Dn

Assembler

Syntax: BFEXTS < ea > {offset:width},Dn

Attributes: Unsized

Description: Extracts a bit ﬁeld from the speciﬁed effective address location, sign extends

to 32 bits, and loads the result into the destination data register. The ﬁeld offset and

ﬁeld width select the bit ﬁeld. The ﬁeld offset speciﬁes the starting bit of the ﬁeld. The

ﬁeld width determines the number of bits in the ﬁeld.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the ﬁeld is set; cleared otherwise.

Z — Set if all bits of the ﬁeld are zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—

1514131211109876543210

1110101111

EFFECTIVE ADDRESS

MODE REGISTER

0 REGISTER Do OFFSET Dw WIDTH

Integer Instructions

4-38 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BFEXTS Extract Bit Field Signed BFEXTS

(MC68020, MC68030, MC68040)

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the base location for the bit ﬁeld. Only data register

direct or control addressing modes can be used as listed in the following table:

Do ﬁeld—Determines how the ﬁeld offset is speciﬁed.

0 — The offset ﬁeld contains the bit ﬁeld offset.

1 — Bits 8 – 6 of the extension word specify a data register that contains the offset;

bits 10 – 9 are zero.

Offset ﬁeld—Speciﬁes the ﬁeld offset, depending on Do.

If Do = 0, the offset ﬁeld is an immediate operand; the operand value is in the range

of 0 – 31.

If Do = 1, the offset ﬁeld speciﬁes a data register that contains the offset. The value

is in the range of – 2

to 2

– 1.

Dw ﬁeld—Determines how the ﬁeld width is speciﬁed.

0 — The width ﬁeld contains the bit ﬁeld width.

1 — Bits 2 – 0 of the extension word specify a data register that contains the width;

bits 4 – 3 are zero.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-39

BFEXTS Extract Bit Field Signed BFEXTS

(MC68020, MC68030, MC68040)

Width ﬁeld—Speciﬁes the ﬁeld width, depending on Dw.

If Dw = 0, the width ﬁeld is an immediate operand; operand values in the range of 1

– 31 specify a ﬁeld width of 1 – 31, and a value of zero speciﬁes a width of 32.

If Dw = 1, the width ﬁeld speciﬁes a data register that contains the width. The value

is modulo 32; values of 1 – 31 specify ﬁeld widths of 1 – 31, and a value of zero

speciﬁes a width of 32.

Integer Instructions

4-40 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BFEXTU Extract Bit Field Unsigned BFEXTU

(MC68020, MC68030, MC68040)

Operation: < bit offset > of Source → Dn

Assembler

Syntax: BFEXTU < ea > {offset:width},Dn

Attributes: Unsized

Description: Extracts a bit ﬁeld from the speciﬁed effective address location, zero extends

to 32 bits, and loads the results into the destination data register. The ﬁeld offset and

ﬁeld width select the ﬁeld. The ﬁeld offset speciﬁes the starting bit of the ﬁeld. The ﬁeld

width determines the number of bits in the ﬁeld.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the source ﬁeld is set; cleared otherwise.

Z — Set if all bits of the ﬁeld are zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—

1514131211109876543210

1110100111

EFFECTIVE ADDRESS

MODE REGISTER

0 REGISTER Do OFFSET Dw WIDTH

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-41

BFEXTU Extract Bit Field Unsigned BFEXTU

(MC68020, MC68030, MC68040)

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the base location for the bit ﬁeld. Only data register

direct or control addressing modes can be used as listed in the following table:

Do ﬁeld—Determines how the ﬁeld offset is speciﬁed.

0 — The offset ﬁeld contains the bit ﬁeld offset.

1 — Bits 8 – 6 of the extension word specify a data register that contains the offset;

bits 10 – 9 are zero.

Offset ﬁeld—Speciﬁes the ﬁeld offset, depending on Do.

If Do = 0, the offset ﬁeld is an immediate operand; the operand value is in the range

of 0 – 31.

If Do = 1, the offset ﬁeld speciﬁes a data register that contains the offset. The value

is in the range of – 2

to 2

– 1.

Dw ﬁeld—Determines how the ﬁeld width is speciﬁed.

0 — The width ﬁeld contains the bit ﬁeld width.

1 — Bits 2 – 0 of the extension word specify a data register that contains the width;

bits 4 – 3 are zero.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-42 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BFEXTU Extract Bit Field Unsigned BFEXTU

(MC68020, MC68030, MC68040)

Width ﬁeld—Speciﬁes the ﬁeld width, depending on Dw.

If Dw = 0, the width ﬁeld is an immediate operand; operand values in the range of 1

– 31 specify a ﬁeld width of 1 – 31, and a value of zero speciﬁes a width of 32.

If Dw = 1, the width ﬁeld speciﬁes a data register that contains the width. The value

is modulo 32; values of 1 – 31 specify ﬁeld widths of 1 – 31, and a value of zero

speciﬁes a width of 32.

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-43

BFFFO Find First One in Bit Field BFFFO

(MC68020, MC68030, MC68040)

Operation: < bit offset > of Source Bit Scan → Dn

Assembler

Syntax: BFFFO < ea > {offset:width},Dn

Attributes: Unsized

Description: Searches the source operand for the most signiﬁcant bit that is set to a value

of one. The bit offset of that bit (the bit offset in the instruction plus the offset of the ﬁrst

one bit) is placed in Dn. If no bit in the bit ﬁeld is set to one, the value in Dn is the ﬁeld

offset plus the ﬁeld width. The instruction sets the condition codes according to the bit

ﬁeld value. The ﬁeld offset and ﬁeld width select the ﬁeld. The ﬁeld offset speciﬁes the

starting bit of the ﬁeld. The ﬁeld width determines the number of bits in the ﬁeld.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the ﬁeld is set; cleared otherwise.

Z — Set if all bits of the ﬁeld are zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—

1514131211109876543210

1110100111

EFFECTIVE ADDRESS

MODE REGISTER

0 REGISTER Do OFFSET Dw WIDTH

Integer Instructions

4-44 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BFFFO Find First One in Bit Field BFFFO

(MC68020, MC68030, MC68040)

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the base location for the bit ﬁeld. Only data register

direct or control addressing modes can be used as listed in the following table:

Do ﬁeld—Determines how the ﬁeld offset is speciﬁed.

0 — The offset ﬁeld contains the bit ﬁeld offset.

1 — Bits 8 – 6 of the extension word specify a data register that contains the offset;

bits 10 – 9 are zero.

Offset ﬁeld—Speciﬁes the ﬁeld offset, depending on Do.

If Do = 0, the offset ﬁeld is an immediate operand; the operand value is in the range

of 0 – 31.

If Do = 1, the offset ﬁeld speciﬁes a data register that contains the offset. The value

is in the range of – 2

to 2

– 1.

Dw ﬁeld—Determines how the ﬁeld width is speciﬁed.

0 — The width ﬁeld contains the bit ﬁeld width.

1 — Bits 2 – 0 of the extension word specify a data register that contains the width;

bits 4 – 3 are zero.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-45

BFFFO Find First One in Bit Field BFFFO

(MC68020, MC68030, MC68040)

Width ﬁeld—Speciﬁes the ﬁeld width, depending on Dw.

If Dw = 0, the width ﬁeld is an immediate operand; operand values in the range of 1

– 31 specify a ﬁeld width of 1 – 31, and a value of zero speciﬁes a width of 32.

If Dw = 1, the width ﬁeld speciﬁes a data register that contains the width. The value

is modulo 32; values of 1 – 31 specify ﬁeld widths of 1 – 31, and a value of zero

speciﬁes a width of 32.

Integer Instructions

4-46 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BFINS Insert Bit Field BFINS

(MC68020, MC68030, MC68040)

Operation: Dn → < bit ﬁeld > of Destination

Assembler

Syntax: BFINS Dn, < ea > {offset:width}

Attributes: Unsized

Description: Inserts a bit ﬁeld taken from the low-order bits of the speciﬁed data register

into a bit ﬁeld at the effective address location. The instruction sets the condition codes

according to the inserted value. The ﬁeld offset and ﬁeld width select the ﬁeld. The ﬁeld

offset speciﬁes the starting bit of the ﬁeld. The ﬁeld width determines the number of bits

in the ﬁeld.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the ﬁeld is set; cleared otherwise.

Z — Set if all bits of the ﬁeld are zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—

1514131211109876543210

1110111111

EFFECTIVE ADDRESS

MODE REGISTER

0 REGISTER Do OFFSET Dw WIDTH

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-47

BFINS Insert Bit Field BFINS

(MC68020, MC68030, MC68040)

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the base location for the bit ﬁeld. Only data register

direct or control alterable addressing modes can be used as listed in the following

table:

Do ﬁeld—Determines how the ﬁeld offset is speciﬁed.

0 — The offset ﬁeld contains the bit ﬁeld offset.

1 — Bits 8 – 6 of the extension word specify a data register that contains the offset;

bits 10 – 9 are zero.

Offset ﬁeld—Speciﬁes the ﬁeld offset, depending on Do.

If Do = 0, the offset ﬁeld is an immediate operand; the operand value is in the range

of 0 – 31.

If Do = 1, the offset ﬁeld speciﬁes a data register that contains the offset. The value

is in the range of – 2

to 2

– 1.

Dw ﬁeld—Determines how the ﬁeld width is speciﬁed.

0 — The width ﬁeld contains the bit ﬁeld width.

1 — Bits 2 – 0 of the extension word specify a data register that contains the width;

bits 4 – 3 are zero.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-48 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BFINS Insert Bit Field BFINS

(MC68020, MC68030, MC68040)

Width ﬁeld—Speciﬁes the ﬁeld width, depending on Dw.

If Dw = 0, the width ﬁeld is an immediate operand; operand values in the range of 1

– 31 specify a ﬁeld width of 1 – 31, and a value of zero speciﬁes a width of 32.

If Dw = 1, the width ﬁeld speciﬁes a data register that contains the width. The value

is modulo 32; values of 1 – 31 specify ﬁeld widths of 1 – 31, and a value of zero

speciﬁes a width of 32.

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-49

BFSET Test Bit Field and Set BFSET

(MC68020, MC68030, MC68040)

Operation: 1 → < bit ﬁeld > of Destination

Assembler

Syntax: BFSET < ea > {offset:width}

Attributes: Unsized

Description: Sets the condition codes according to the value in a bit ﬁeld at the speciﬁed

effective address, then sets each bit in the ﬁeld.

The field offset and the field width select the field. The field offset specifies the starting

bit of the field. The field width determines the number of bits in the field.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the ﬁeld is set; cleared otherwise.

Z — Set if all bits of the ﬁeld are zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—

1514131211109876543210

1110111011

EFFECTIVE ADDRESS

MODE REGISTER

0000Do OFFSET Dw WIDTH

Integer Instructions

4-50 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BFSET Test Bit Field and Set BFSET

(MC68020, MC68030, MC68040)

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the base location for the bit ﬁeld. Only data register

direct or control alterable addressing modes can be used as listed in the following

table:

Do ﬁeld—Determines how the ﬁeld offset is speciﬁed.

0 — The offset ﬁeld contains the bit ﬁeld offset.

1 — Bits 8 – 6 of the extension word specify a data register that contains the offset;

bits 10 – 9 are zero.

Offset ﬁeld—Speciﬁes the ﬁeld offset, depending on Do.

If Do = 0, the offset ﬁeld is an immediate operand; the operand value is in the range

of 0 – 31.

If Do = 1, the offset ﬁeld speciﬁes a data register that contains the offset. The value

is in the range of – 2

to 2

– 1.

Dw ﬁeld—Determines how the ﬁeld width is speciﬁed.

0 — The width ﬁeld contains the bit ﬁeld width.

1 — Bits 2 – 0 of the extension word specify a data register that contains the width;

bits 4 – 3 are zero.

Width ﬁeld—Speciﬁes the ﬁeld width, depending on Dw.

If Dw = 0, the width ﬁeld is an immediate operand; operand values in the range of 1

– 31 specify a ﬁeld width of 1 – 31, and a value of zero speciﬁes a width of 32.

If Dw = 1, the width ﬁeld speciﬁes a data register that contains the width. The value

is modulo 32; values of 1 – 31 specify ﬁeld widths of 1 – 31, and a value of zero

speciﬁes a width of 32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-51

BFTST Test Bit Field BFTST

(MC68020, MC68030, MC68040)

Operation: < bit ﬁeld > of Destination

Assembler

Syntax: BFTST < ea > {offset:width}

Attributes: Unsized

Description: Sets the condition codes according to the value in a bit ﬁeld at the speciﬁed

effective address location. The ﬁeld offset and ﬁeld width select the ﬁeld. The ﬁeld offset

speciﬁes the starting bit of the ﬁeld. The ﬁeld width determines the number of bits in the

ﬁeld.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the ﬁeld is set; cleared otherwise.

Z — Set if all bits of the ﬁeld are zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—∗∗00

1514131211109876543210

1110100011

EFFECTIVE ADDRESS

MODE REGISTER

0000Do OFFSET Dw WIDTH

Integer Instructions

4-52 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BFTST Test Bit Field BFTST

(MC68020, MC68030, MC68040)

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the base location for the bit ﬁeld. Only data register

direct or control addressing modes can be used as listed in the following table:

Do ﬁeld—Determines how the ﬁeld offset is speciﬁed.

0 — The offset ﬁeld contains the bit ﬁeld offset.

1 — Bits 8 – 6 of the extension word specify a data register that contains the offset;

bits 10 – 9 are zero.

Offset ﬁeld—Speciﬁes the ﬁeld offset, depending on Do.

If Do = 0, the offset ﬁeld is an immediate operand; the operand value is in the range

of 0 – 31.

If Do = 1, the offset ﬁeld speciﬁes a data register that contains the offset. The value

is in the range of – 2

to 2

– 1.

Dw ﬁeld—Determines how the ﬁeld width is speciﬁed.

0 — The width ﬁeld contains the bit ﬁeld width.

1 — Bits 2 – 0 of the extension word specify a data register that contains the width;

bits 4 – 3 are zero.

Width ﬁeld—Speciﬁes the ﬁeld width, depending on Dw.

If Dw = 0, the width ﬁeld is an immediate operand, operand values in the range of 1

– 31 specify a ﬁeld width of 1 – 31, and a value of zero speciﬁes a width of 32.

If Dw = 1, the width ﬁeld speciﬁes a data register that contains the width. The value

is modulo 32; values of 1 – 31 specify ﬁeld widths of 1 – 31, and a value of zero

speciﬁes a width of 32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-53

BKPT Breakpoint BKPT

(MC68EC000, MC68010, MC68020, MC68030, MC68040, CPU32)

Operation: Run Breakpoint Acknowledge Cycle; TRAP As Illegal Instruction

Assembler

Syntax: BKPT # < data >

Attributes: Unsized

Description: For the MC68010, a breakpoint acknowledge bus cycle is run with function

codes driven high and zeros on all address lines. Whether the breakpoint acknowledge

bus cycle is terminated with DT

ACK, BERR, or VPA, the processor always takes an

illegal instruction exception. During exception processing, a debug monitor can

distinguish different software breakpoints by decoding the ﬁeld in the BKPT instruction.

For the MC68000 and MC68008, the breakpoint cycle is not run, but an illegal

instruction exception is taken.

For the MC68020, MC68030, and CPU32, a breakpoint acknowledge bus cycle is exe-

cuted with the immediate data (value 0 – 7) on bits 2 – 4 of the address bus and zeros

on bits 0 and 1 of the address bus. The breakpoint acknowledge bus cycle accesses

the CPU space, addressing type 0, and provides the breakpoint number specified by

the instruction on address lines A2 – A4. If the external hardware terminates the cycle

with DSACKx

or STERM, the data on the bus (an instruction word) is inserted into the

instruction pipe and is executed after the breakpoint instruction. The breakpoint instruc-

tion requires a word to be transferred so, if the first bus cycle accesses an 8- bit port,

a second bus cycle is required. If the external logic terminates the breakpoint acknowl-

edge bus cycle with BERR

(i.e., no instruction word available), the processor takes an

illegal instruction exception.

For the MC68040, this instruction executes a breakpoint acknowledge bus cycle.

Regardless of the cycle termination, the MC68040 takes an illegal instruction excep-

tion.

For more information on the breakpoint instruction refer to the appropriate user’s man-

ual on bus operation.

This instruction supports breakpoints for debug monitors and real- time hardware emu-

lators.

Integer Instructions

4-54 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BKPT Breakpoint BKPT

(MC68EC000, MC68010, MC68020,

MC68030, MC68040, CPU32)

Condition Codes:

Not affected.

Instruction Format:

Instruction Field:

Vector ﬁeld—Contains the immediate data, a value in the range of 0 – 7. This is the

breakpoint number.

1514131211109876543210

0100100001001 VECTOR

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-55

BRA Branch Always BRA

(M68000 Family)

Operation: PC + d

→ PC

Assembler

Syntax: BRA < label >

Attributes: Size = (Byte, Word, Long*)

*(MC68020, MC68030, MC68040 only)

Description: Program execution continues at location (PC) + displacement. The program

counter contains the address of the instruction word of the BRA instruction plus two.

The displacement is a twos complement integer that represents the relative distance in

bytes from the current program counter to the destination program counter. If the 8-bit

displacement ﬁeld in the instruction word is zero, a 16-bit displacement (the word

immediately following the instruction) is used. If the 8-bit displacement ﬁeld in the

instruction word is all ones ($FF), the 32-bit displacement (long word immediately

following the instruction) is used.

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

8-Bit Displacement ﬁeld—Twos complement integer specifying the number of bytes

between the branch instruction and the next instruction to be executed.

16-Bit Displacement ﬁeld—Used for a larger displacement when the 8-bit displacement

is equal to $00.

32-Bit Displacement ﬁeld—Used for a larger displacement when the 8-bit displacement

is equal to $FF.

NOTE

A branch to the immediately following instruction automatically

uses the 16-bit displacement format because the 8-bit

displacement ﬁeld contains $00 (zero offset).

1514131211109876543210

01100000 8-BIT DISPLACEMENT

16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00

32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF

Integer Instructions

4-56 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BSET Test a Bit and Set BSET

(M68000 Family)

Operation: TEST ( < bit number > of Destination) → Z; 1 → < bit number > of Des-

tination

Assembler BSET Dn, < ea >

Syntax: BSET # < data > , < ea >

Attributes: Size = (Byte, Long)

Description: Tests a bit in the destination operand and sets the Z condition code

appropriately, then sets the speciﬁed bit in the destination operand. When a data

number. When a memory location is the destination, the operation is a byte operation,

and the bit number is modulo 8. In all cases, bit zero refers to the least signiﬁcant bit.

The bit number for this operation can be speciﬁed in either of two ways:

1. Immediate—The bit number is specified in the second word of the instruction.

2. Register—The specified data register contains the bit number.

Condition Codes:

X — Not affected.

N — Not affected.

Z — Set if the bit tested is zero; cleared otherwise.

V — Not affected.

C — Not affected.

XNZVC

—— ∗ ——

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-57

BSET Test a Bit and Set BSET

(M68000 Family)

Instruction Format:

BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the destination location. Only data alterable

addressing modes can be used as listed in the following tables:

*Long only; all others are byte only.

**Can be used with CPU32.

1514131211109876543210

0000 REGISTER 1 1 1

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)† — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-58 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BSET Test a Bit and Set BSET

(M68000 Family)

Instruction Format:

BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the destination location. Only data alterable

addressing modes can be used as listed in the following tables:

*Long only; all others are byte only.

**Can be used with CPU32.

Bit Number ﬁeld—Speciﬁes the bit number.

1514131211109876543210

0000100011

EFFECTIVE ADDRESS

MODE REGISTER

0000000 BIT NUMBER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)† — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-59

BSR Branch to Subroutine BSR

(M68000 Family)

Operation: SP – 4 → SP; PC → (SP); PC + d

→ PC

Assembler

Syntax: BSR < label >

Attributes: Size = (Byte, Word, Long*)

*(MC68020, MC68030, MC68040 only)

Description: Pushes the long-word address of the instruction immediately following the

BSR instruction onto the system stack. The program counter contains the address of

the instruction word plus two. Program execution then continues at location (PC) +

displacement. The displacement is a twos complement integer that represents the

relative distance in bytes from the current program counter to the destination program

counter. If the 8-bit displacement ﬁeld in the instruction word is zero, a 16-bit

displacement (the word immediately following the instruction) is used. If the 8-bit

displacement ﬁeld in the instruction word is all ones ($FF), the 32-bit displacement

(long word immediately following the instruction) is used.

Condition Codes:

Not affected.

Instruction Format:

1514131211109876543210

01100001 8-BIT DISPLACEMENT

16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00

32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF

Integer Instructions

4-60 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BSR Branch to Subroutine BSR

(M68000 Family)

Instruction Fields:

8-Bit Displacement ﬁeld—Twos complement integer specifying the number of bytes

between the branch instruction and the next instruction to be executed.

16-Bit Displacement ﬁeld—Used for a larger displacement when the 8-bit displacement

is equal to $00.

32-Bit Displacement ﬁeld—Used for a larger displacement when the 8-bit displacement

is equal to $FF.

NOTE

A branch to the immediately following instruction automatically

uses the 16-bit displacement format because the 8-bit

displacement ﬁeld contains $00 (zero offset).

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-61

BTST Test a Bit BTST

(M68000 Family)

Operation: TEST ( < bit number > of Destination) → Z

Assembler BTST Dn, < ea >

Syntax: BTST # < data > , < ea >

Attributes: Size = (Byte, Long)

Description: Tests a bit in the destination operand and sets the Z condition code

appropriately. When a data register is the destination, any of the 32 bits can be

speciﬁed by a modulo 32- bit number. When a memory location is the destination, the

operation is a byte operation, and the bit number is modulo 8. In all cases, bit zero

refers to the least signiﬁcant bit. The bit number for this operation can be speciﬁed in

either of two ways:

1. Immediate—The bit number is specified in a second word of the instruction.

2. Register—The specified data register contains the bit number.

Condition Codes:

X — Not affected.

N — Not affected.

Z — Set if the bit tested is zero; cleared otherwise.

V — Not affected.

C — Not affected.

XNZVC

—— ∗ ——

Integer Instructions

4-62 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

BTST Test a Bit BTST

(M68000 Family)

Instruction Format:

BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the destination location. Only data addressing

modes can be used as listed in the following tables:

*Long only; all others are byte only.

**Can be used with CPU32.

1514131211109876543210

0000 REGISTER 1 0 0

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn* 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)† 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-63

BTST Test a Bit BTST

(M68000 Family)

Instruction Format:

BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the destination location. Only data addressing

modes can be used as listed in the following tables:

*Can be used with CPU32.

Bit Number ﬁeld—Speciﬁes the bit number.

1514131211109876543210

0000100000

EFFECTIVE ADDRESS

MODE REGISTER

00000000 BIT NUMBER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-64 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

CALLM Call Module CALLM

(MC68020)

Operation: Save Current Module State on Stack; Load New Module State from

Destination

Assembler

Syntax: CALLM # < data > , < ea >

Attributes: Unsized

Description: The effective address of the instruction is the location of an external module

descriptor. A module frame is created on the top of the stack, and the current module

state is saved in the frame. The immediate operand speciﬁes the number of bytes of

arguments to be passed to the called module. A new module state is loaded from the

descriptor addressed by the effective address.

Condition Codes:

Not affected.

Instruction Format:

1514131211109876543210

0000011011

EFFECTIVE ADDRESS

MODE REGISTER

00000000 ARGUMENT COUNT

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-65

CALLM Call Module CALLM

(MC68020)

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the address of the module descriptor. Only control

addressing modes can be used as listed in the following table:

Argument Count ﬁeld—Speciﬁes the number of bytes of arguments to be passed to the

called module. The 8-bit ﬁeld can specify from 0 to 255 bytes of arguments. The

same number of bytes is removed from the stack by the RTM instruction.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-66 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

CAS CAS

CAS2 Compare and Swap with Operand CAS2

(MC68020, MC68030, MC68040)

Operation: CAS Destination – Compare Operand → cc;

If Z, Update Operand → Destination

Else Destination → Compare Operand

CAS2 Destination 1 – Compare 1 → cc;

If Z, Destination 2 – Compare 2 → cc

If Z, Update 1 → Destination 1; Update 2 → Destination 2

Else Destination 1 → Compare 1; Destination 2 → Compare 2

Assembler CAS Dc,Du, < ea >

Syntax: CAS2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2)

Attributes: Size = (Byte

, Word, Long)

Description: CAS compares the effective address operand to the compare operand (Dc).

If the operands are equal, the instruction writes the update operand (Du) to the effective

address operand; otherwise, the instruction writes the effective address operand to the

compare operand (Dc).

CAS2 compares memory operand 1 (Rn1) to compare operand 1 (Dc1). If the oper-

ands are equal, the instruction compares memory operand 2 (Rn2) to compare oper-

and 2 (Dc2). If these operands are also equal, the instruction writes the update

operands (Du1 and Du2) to the memory operands (Rn1 and Rn2). If either comparison

fails, the instruction writes the memory operands (Rn1 and Rn2) to the compare oper-

ands (Dc1 and Dc2).

Both operations access memory using locked or read-modify-write transfer sequences,

providing a means of synchronizing several processors.

Condition Codes:

X — Not affected.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if an overﬂow is generated; cleared otherwise.

C — Set if a borrow is generated; cleared otherwise.

CAS2 cannot use byte operands.

XNZVC

—∗∗∗∗

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-67

CAS CAS

CAS2 Compare and Swap with Operand CAS2

(MC68020, MC68030, MC68040)

Instruction Format:

CAS

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

01 — Byte operation

10 — Word operation

11 — Long operation

Effective Address ﬁeld—Speciﬁes the location of the memory operand. Only memory

alterable addressing modes can be used as listed in the following table:

Du ﬁeld—Speciﬁes the data register that contains the update value to be written to the

memory operand location if the comparison is successful.

Dc ﬁeld—Speciﬁes the data register that contains the value to be compared to the

memory operand.

1514131211109876543210

00001 SIZE 0 1 1

EFFECTIVE ADDRESS

MODE REGISTER

0000000 Du 000 Dc

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-68 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

CAS CAS

CAS2 Compare and Swap with Operand CAS2

(MC68020, MC68030, MC68040)

Instruction Format:

CAS2

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

10 — Word operation

11 — Long operation

D/A1, D/A2 ﬁelds—Specify whether Rn1 and Rn2 reference data or address registers,

respectively.

0 — The corresponding register is a data register.

1 — The corresponding register is an address register.

Rn1, Rn2 ﬁelds—Specify the numbers of the registers that contain the addresses of

the ﬁrst and second memory operands, respectively. If the operands overlap in

memory, the results of any memory update are undeﬁned.

Du1, Du2 ﬁelds—Specify the data registers that contain the update values to be written

to the ﬁrst and second memory operand locations if the comparison is successful.

Dc1, Dc2 ﬁelds—Specify the data registers that contain the test values to be compared

to the ﬁrst and second memory operands, respectively. If Dc1 and Dc2 specify the

same data register and the comparison fails, memory operand 1 is stored in the

data register.

NOTE

The CAS and CAS2 instructions can be used to perform secure

update operations on system control data structures in a

multiprocessing environment.

In the MC68040 if the operands are not equal, the destination or

destination 1 operand is written back to memory to complete the

locked access for CAS or CAS2, respectively.

1514131211109876543210

00001 SIZE 011111100

D/A1 Rn1 0 0 0 Du1 0 0 0 Dc1

D/A2 Rn2 0 0 0 Du2 0 0 0 Dc2

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-69

CHK Check Register Against Bounds CHK

(M68000 Family)

Operation: If Dn < 0 or Dn > Source

Then TRAP

Assembler

Syntax: CHK < ea > ,Dn

Attributes: Size = (Word, Long*)

*(MC68020, MC68030, MC68040 only)

Description: Compares the value in the data register speciﬁed in the instruction to zero and

to the upper bound (effective address operand). The upper bound is a twos

complement integer. If the register value is less than zero or greater than the upper

bound, a CHK instruction exception (vector number 6) occurs.

Condition Codes:

X — Not affected.

N — Set if Dn < 0; cleared if Dn > effective address operand; undeﬁned otherwise.

Z — Undeﬁned.

V — Undeﬁned.

C — Undeﬁned.

Instruction Format:

XNZVC

—∗UUU

1514131211109876543210

0100 REGISTER SIZE 0

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

4-70 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

CHK Check Register Against Bounds CHK

(M68000 Family)

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

11— Word operation

10— Long operation

Effective Address ﬁeld—Speciﬁes the upper bound operand. Only data addressing

modes can be used as listed in the following tables:

*Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-71

CHK2 Check Register Against Bounds CHK2

(MC68020, MC68030, MC68040, CPU32)

Operation: If Rn < LB or Rn > UB

Then TRAP

Assembler

Syntax: CHK2 < ea > ,Rn

Attributes: Size = (Byte, Word, Long)

Description: Compares the value in Rn to each bound. The effective address contains the

bounds pair: the upper bound following the lower bound. For signed comparisons, the

arithmetically smaller value should be used as the lower bound. For unsigned

comparisons, the logically smaller value should be the lower bound.

The size of the data and the bounds can be specified as byte, word, or long. If Rn is a

data register and the operation size is byte or word, only the appropriate low-order part

of Rn is checked. If Rn is an address register and the operation size is byte or word,

the bounds operands are sign-extended to 32 bits, and the resultant operands are

compared to the full 32 bits of An.

If the upper bound equals the lower bound, the valid range is a single value. If the reg-

ister value is less than the lower bound or greater than the upper bound, a CHK instruc-

tion exception (vector number 6) occurs.

Condition Codes:

X — Not affected.

N — Undeﬁned.

Z — Set if Rn is equal to either bound; cleared otherwise.

V — Undeﬁned.

C — Set if Rn is out of bounds; cleared otherwise.

XNZVC

—U ∗ U ∗

Integer Instructions

4-72 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

CHK2 Check Register Against Bounds CHK2

(MC68020, MC68030, MC68040, CPU32)

Instruction Format:

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

Effective Address ﬁeld—Speciﬁes the location of the bounds operands. Only control

addressing modes can be used as listed in the following tables:

D/A ﬁeld—Speciﬁes whether an address register or data register is to be checked.

0 — Data register

1 — Address register

checked.

1514131211109876543210

00000 SIZE 0 1 1

EFFECTIVE ADDRESS

MODE REGISTER

D/A REGISTER 100000000000

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-73

CLR Clear an Operand CLR

(M68000 Family)

Operation: 0 → Destination

Assembler

Syntax: CLR < ea >

Attributes: Size = (Byte, Word, Long)

Description: Clears the destination operand to zero. The size of the operation may be

speciﬁed as byte, word, or long.

Condition Codes:

X — Not affected.

N — Always cleared.

Z — Always set.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—0100

151413121110987 6543210

01000010 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

4-74 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

CLR Clear an Operand CLR

(M68000 Family)

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00—Byte operation

01—Word operation

10—Long operation

Effective Address ﬁeld—Speciﬁes the destination location. Only data alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

NOTE

In the MC68000 and MC68008 a memory location is read before

it is cleared.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-75

CMP Compare CMP

(M68000 Family)

Operation: Destination – Source → cc

Assembler

Syntax: CMP < ea > , Dn

Attributes: Size = (Byte, Word, Long)

Description: Subtracts the source operand from the destination data register and sets the

condition codes according to the result; the data register is not changed. The size of

the operation can be byte, word, or long.

Condition Codes:

X — Not affected.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if an overﬂow occurs; cleared otherwise.

C — Set if a borrow occurs; cleared otherwise.

Instruction Format:

Instruction Fields:

Opmode ﬁeld

XNZVC

—∗∗∗∗

1514131211109876543210

1011 REGISTER OPMODE

EFFECTIVE ADDRESS

MODE REGISTER

Byte Word Long Operation

000 001 010 Dn – < ea >

Integer Instructions

4-76 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

CMP Compare CMP

(M68000 Family)

Effective Address ﬁeld—Speciﬁes the source operand. All addressing modes can be

used as listed in the following tables:

*Word and Long only.

**Can be used with CPU32.

NOTE

CMPA is used when the destination is an address register. CMPI

is used when the source is immediate data. CMPM is used for

memory-to-memory compares. Most assemblers automatically

make the distinction.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An* 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)† 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-77

CMPA Compare Address CMPA

(M68000 Family)

Operation: Destination – Source → cc

Assembler

Syntax: CMPA < ea > , An

Attributes: Size = (Word, Long)

Description: Subtracts the source operand from the destination address register and sets

the condition codes according to the result; the address register is not changed. The

size of the operation can be speciﬁed as word or long. Word length source operands

are sign- extended to 32 bits for comparison.

Condition Codes:

X — Not affected.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if an overﬂow is generated; cleared otherwise.

C — Set if a borrow is generated; cleared otherwise.

Instruction Format:

XNZVC

—∗∗∗∗

1514131211109876543210

1011 REGISTER OPMODE

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

4-78 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

CMPA Compare Address CMPA

(M68000 Family)

Instruction Fields:

Opmode ﬁeld—Speciﬁes the size of the operation.

011—Word operation; the source operand is sign-extended to a long operand, and

the operation is performed on the address register using all 32 bits.

111— Long operation.

Effective Address ﬁeld—Speciﬁes the source operand. All addressing modes can be

used as listed in the following tables:

*Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-79

CMPI Compare Immediate CMPI

(M68000 Family)

Operation: Destination – Immediate Data → cc

Assembler

Syntax: CMPI # < data > , < ea >

Attributes: Size = (Byte, Word, Long)

Description: Subtracts the immediate data from the destination operand and sets the

condition codes according to the result; the destination location is not changed. The

size of the operation may be speciﬁed as byte, word, or long. The size of the immediate

data matches the operation size.

Condition Codes:

X — Not affected.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if an overﬂow occurs; cleared otherwise.

C — Set if a borrow occurs; cleared otherwise.

Instruction Format:

XNZVC

—∗∗∗∗

1514131211109876543210

00001100 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

16-BIT WORD DATA 8-BIT BYTE DATA

32-BIT LONG DATA

Integer Instructions

4-80 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

CMPI Compare Immediate CMPI

(M68000 Family)

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

Effective Address ﬁeld—Speciﬁes the destination operand. Only data addressing

modes can be used as listed in the following tables:

*PC relative addressing modes do not apply to MC68000, MC680008, or MC6801.

**Can be used with CPU32.

Immediate ﬁeld—Data immediately following the instruction.

If size = 00, the data is the low-order byte of the immediate word.

If size = 01, the data is the entire immediate word.

If size = 10, the data is the next two immediate words.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC)* 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn)* 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)† 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-81

CMPM Compare Memory CMPM

(M68000 Family)

Operation: Destination – Source → cc

Assembler

Syntax: CMPM (Ay) + ,(Ax) +

Attributes: Size = (Byte, Word, Long)

Description: Subtracts the source operand from the destination operand and sets the

condition codes according to the results; the destination location is not changed. The

operands are always addressed with the postincrement addressing mode, using the

address registers speciﬁed in the instruction. The size of the operation may be

speciﬁed as byte, word, or long.

Condition Codes:

X — Not affected.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if an overﬂow is generated; cleared otherwise.

C — Set if a borrow is generated; cleared otherwise.

Instruction Format:

Instruction Fields:

postincrement addressing mode.

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

postincrement addressing mode.

XNZVC

—∗∗∗∗

1514131211109876543210

1011 REGISTER Ax 1 SIZE 0 0 1 REGISTER Ay

Integer Instructions

4-82 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

CMP2 Compare Register Against Bounds CMP2

(MC68020, MC68030, MC68040, CPU32)

Operation: Compare Rn < LB or Rn > UB and Set Condition Codes

Assembler

Syntax: CMP2 < ea > ,Rn

Attributes: Size = (Byte, Word, Long)

Description: Compares the value in Rn to each bound. The effective address contains the

bounds pair: upper bound following the lower bound. For signed comparisons, the

arithmetically smaller value should be used as the lower bound. For unsigned

comparisons, the logically smaller value should be the lower bound.

The size of the data and the bounds can be specified as byte, word, or long. If Rn is a

data register and the operation size is byte or word, only the appropriate low-order part

of Rn is checked. If Rn is an address register and the operation size is byte or word,

the bounds operands are sign-extended to 32 bits, and the resultant operands are

compared to the full 32 bits of An.

If the upper bound equals the lower bound, the valid range is a single value.

NOTE

This instruction is identical to CHK2 except that it sets condition

codes rather than taking an exception when the value in Rn is

out of bounds.

Condition Codes:

X — Not affected.

N — Undeﬁned.

Z — Set if Rn is equal to either bound; cleared otherwise.

V — Undeﬁned.

C — Set if Rn is out of bounds; cleared otherwise.

XNZVC

—U ∗ U ∗

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-83

CMP2 Compare Register Against Bounds CMP2

(MC68020, MC68030, MC68040, CPU32)

Instruction Format:

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

Effective Address ﬁeld—Speciﬁes the location of the bounds pair. Only control

addressing modes can be used as listed in the following tables:

D/A ﬁeld—Speciﬁes whether an address register or data register is compared.

0 — Data register

1 — Address register

checked.

1514131211109876543210

00000 SIZE 0 1 1

EFFECTIVE ADDRESS

MODE REGISTER

D/A REGISTER 000000000000

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-84 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

cpBcc Branch on Coprocessor Condition cpBcc

(MC68020, MC68030)

Operation: If cpcc True

Then Scan PC + d

→ PC

Assembler

Syntax: cpBcc < label >

Attributes: Size = (Word, Long)

Description: If the speciﬁed coprocessor condition is true, program execution continues at

location scan PC + displacement. The value of the scan PC is the address of the ﬁrst

displacement word. The displacement is a twos complement integer that represents

the relative distance in bytes from the scan PC to the destination program counter. The

displacement can be either 16 or 32 bits. The coprocessor determines the speciﬁc

condition from the condition ﬁeld in the operation word.

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Identiﬁes the coprocessor for this operation. Coprocessor ID of

000 results in an F-line exception for the MC68030.

Size ﬁeld—Speciﬁes the size of the displacement.

0 — The displacement is 16 bits.

1 — The displacement is 32 bits.

Coprocessor Condition ﬁeld—Speciﬁes the coprocessor condition to be tested. This

ﬁeld is passed to the coprocessor, which provides directives to the main

processor for processing this instruction.

16-Bit Displacement ﬁeld—The displacement value occupies 16 bits.

32-Bit Displacement ﬁeld—The displacement value occupies 32 bits.

1514131211109876543210

1111

COPROCESSOR

0 1 SIZE COPROCESSOR CONDITION

OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS

WORD OR

LONG-WORD DISPLACEMENT

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-85

cpDBcc Test Coprocessor Condition cpDBcc

Decrement and Branch

(MC68020, MC68030)

Operation: If cpcc False

Then (Dn – 1 → Dn; If Dn ≠ – 1 Then Scan PC + d

→ PC)

Assembler

Syntax: cpDBcc Dn, < label >

Attributes: Size = (Word)

Description: If the speciﬁed coprocessor condition is true, execution continues with the

next instruction. Otherwise, the low-order word in the speciﬁed data register is

decremented by one. If the result is equal to – 1, execution continues with the next

instruction. If the result is not equal to – 1, execution continues at the location indicated

by the value of the scan PC plus the sign-extended 16-bit displacement. The value of

the scan PC is the address of the displacement word. The displacement is a twos

complement integer that represents the relative distance in bytes from the scan PC to

the destination program counter. The coprocessor determines the speciﬁc condition

from the condition word that follows the operation word.

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Identiﬁes the coprocessor for this operation; coprocessor ID of

000 results in an F-line exception for the MC68030.

Coprocessor Condition ﬁeld—Speciﬁes the coprocessor condition to be tested. This

ﬁeld is passed to the coprocessor, which provides directives to the main

processor for processing this instruction.

Displacement ﬁeld—Speciﬁes the distance of the branch (in bytes).

1514131211109876543210

1111

COPROCESSOR

001001 REGISTER

0000000000 COPROCESSOR CONDITION

OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS

16-BIT DISPLACEMENT

Integer Instructions

4-86 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

cpGEN Coprocessor General Function cpGEN

(MC68020, MC68030)

Operation: Pass Command Word to Coprocessor

Assembler

Syntax: cpGEN < parameters as deﬁned by coprocessor >

Attributes: Unsized

Description: Transfers the command word that follows the operation word to the speciﬁed

coprocessor. The coprocessor determines the speciﬁc operation from the command

word. Usually a coprocessor deﬁnes speciﬁc instances of this instruction to provide its

instruction set.

Condition Codes:

May be modiﬁed by coprocessor; unchanged otherwise.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Identiﬁes the coprocessor for this operation; note that

coprocessor ID of 000 is reserved for MMU instructions for the MC68030.

Effective Address ﬁeld—Speciﬁes the location of any operand not resident in the

coprocessor. The allowable addressing modes are determined by the operation

to be performed.

Coprocessor Command ﬁeld—Speciﬁes the coprocessor operation to be performed.

This word is passed to the coprocessor, which in turn provides directives to the

main processor for processing this instruction.

1514131211109876543210

1111

COPROCESSOR

000

EFFECTIVE ADDRESS

MODE REGISTER

COPROCESSOR-DEPENDENT COMMAND WORD

OPTIONAL EFFECTIVE ADDRESS OR COPROCESSOR-DEFINED EXTENSIONWORDS

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-87

cpScc Set on Coprocessor Condition cpScc

(MC68020, MC68030)

Operation: If cpcc True

Then 1s → Destination

Else 0s → Destination

Assembler

Syntax: cpScc < ea >

Attributes: Size = (Byte)

Description: Tests the speciﬁed coprocessor condition code. If the condition is true, the

byte speciﬁed by the effective address is set to TRUE (all ones); otherwise, that byte is

set to FALSE (all zeros). The coprocessor determines the speciﬁc condition from the

condition word that follows the operation word.

Condition Codes:

Not affected.

Instruction Format:

1514131211109876543210

1111

COPROCESSOR

001

EFFECTIVE ADDRESS

MODE REGISTER

0000000000 COPROCESSOR CONDITION

OPTIONAL EFFECTIVE ADDRESS OR COPROCESSOR-DEFINED EXTENSIONWORDS

Integer Instructions

4-88 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

cpScc Set on Coprocessor Condition cpScc

(MC68020, MC68030)

Instruction Fields:

Coprocessor ID ﬁeld—Identiﬁes the coprocessor for this operation. Coprocessor ID of

000 results in an F-line exception for the MC68030.

Effective Address ﬁeld—Speciﬁes the destination location. Only data alterable

addressing modes can be used as listed in the following table:

Coprocessor Condition ﬁeld—Speciﬁes the coprocessor condition to be tested. This

ﬁeld is passed to the coprocessor, which in turn provides directives to the main

processor for processing this instruction.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-89

cpTRAPcc Trap on Coprocessor Condition cpTRAPcc

(MC68020, MC68030)

Operation: If cpcc True

Then TRAP

Assembler cpTRAPcc

Syntax: cpTRAPcc # < data >

Attributes: Unsized or Size = (Word, Long)

Description: Tests the speciﬁed coprocessor condition code; if the selected coprocessor

condition is true, the processor initiates a cpTRAPcc exception, vector number 7. The

program counter value placed on the stack is the address of the next instruction. If the

selected condition is not true, no operation is performed, and execution continues with

the next instruction. The coprocessor determines the speciﬁc condition from the

condition word that follows the operation word. Following the condition word is a user-

deﬁned data operand speciﬁed as immediate data to be used by the trap handler.

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

Coprocessor ID ﬁeld—Identiﬁes the coprocessor for this operation; coprocessor ID of

000 results in an F-line exception for the MC68030.

Opmode ﬁeld—Selects the instruction form.

010—Instruction is followed by one operand word.

011—Instruction is followed by two operand words.

100—Instruction has no following operand words.

Coprocessor Condition ﬁeld—Speciﬁes the coprocessor condition to be tested. This

ﬁeld is passed to the coprocessor, which provides directives to the main

processor for processing this instruction.

1514131211109876543210

1111

COPROCESSOR

001111 OPMODE

0000000000 COPROCESSOR CONDITION

OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS

OPTIONAL WORD

OR LONG-WORD OPERAND

Integer Instructions

4-90 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

DBcc Test Condition, Decrement, and Branch DBcc

(M68000 Family)

Operation: If Condition False

Then (Dn – 1 → Dn; If Dn ≠ – 1 Then PC + d

→ PC)

Assembler

Syntax: DBcc Dn, < label >

Attributes: Size = (Word)

Description: Controls a loop of instructions. The parameters are a condition code, a data

termination; if it is true, no operation is performed. If the termination condition is not

true, the low-order 16 bits of the counter data register decrement by one. If the result

is – 1, execution continues with the next instruction. If the result is not equal to – 1,

execution continues at the location indicated by the current value of the program

counter plus the sign-extended 16-bit displacement. The value in the program counter

is the address of the instruction word of the DBcc instruction plus two. The

displacement is a twos complement integer that represents the relative distance in

bytes from the current program counter to the destination program counter. Condition

code cc speciﬁes one of the following conditional tests (refer to Table 3-19 for more

information on these conditional tests):

Condition Codes:

Not affected.

Mnemonic Condition Mnemonic Condition

CC(HI) Carry Clear LS Low or Same

CS(LO) Carry Set LT Less Than

EQ Equal MI Minus

F False NE Not Equal

GE Greater or Equal PL Plus

GT Greater Than T True

HI High VC Overflow Clear

LE Less or Equal VS Overflow Set

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-91

DBcc Test Condition, Decrement, and Branch DBcc

(M68000 Family)

Instruction Format:

Instruction Fields:

Condition ﬁeld—The binary code for one of the conditions listed in the table.

Displacement ﬁeld—Speciﬁes the number of bytes to branch.

NOTE

The terminating condition is similar to the UNTIL loop clauses of

high-level languages. For example: DBMI can be stated as

"decrement and branch until minus".

Most assemblers accept DBRA for DBF for use when only a

count terminates the loop (no condition is tested).

A program can enter a loop at the beginning or by branching to

the trailing DBcc instruction. Entering the loop at the beginning

is useful for indexed addressing modes and dynamically

speciﬁed bit operations. In this case, the control index count

must be one less than the desired number of loop executions.

However, when entering a loop by branching directly to the

trailing DBcc instruction, the control count should equal the loop

execution count. In this case, if a zero count occurs, the DBcc

instruction does not branch, and the main loop is not executed.

1514131211109876543210

0101 CONDITION 11001 REGISTER

16-BIT DISPLACEMENT

Integer Instructions

4-92 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

DIVS, DIVSL Signed Divide DIVS, DIVSL

(M68000 Family)

Operation: Destination ÷ Source → Destination

Assembler DIVS.W < ea > ,Dn32/16 → 16r – 16q

Syntax: *DIVS.L < ea > ,Dq 32/32 → 32q

*DIVS.L < ea > ,Dr:Dq 64/32 → 32r – 32q

*DIVSL.L < ea > ,Dr:Dq 32/32 → 32r – 32q

*Applies to MC68020, MC68030, MC68040, CPU32 only

Attributes: Size = (Word, Long)

Description: Divides the signed destination operand by the signed source operand and

stores the signed result in the destination. The instruction uses one of four forms. The

word form of the instruction divides a long word by a word. The result is a quotient in

the lower word (least signiﬁcant 16 bits) and a remainder in the upper word (most

signiﬁcant 16 bits). The sign of the remainder is the same as the sign of the dividend.

The first long form divides a long word by a long word. The result is a long quotient; the

remainder is discarded.

The second long form divides a quad word (in any two data registers) by a long word.

The result is a long-word quotient and a long-word remainder.

The third long form divides a long word by a long word. The result is a long-word quo-

tient and a long-word remainder.

Two special conditions may arise during the operation:

1. Division by zero causes a trap.

2. Overflow may be detected and set before the instruction completes. If the in-

struction detects an overflow, it sets the overflow condition code, and the oper-

ands are unaffected.

Condition Codes:

X—Not affected.

N — Set if the quotient is negative; cleared otherwise; undeﬁned if overﬂow or divide

by zero occurs.

Z — Set if the quotient is zero; cleared otherwise; undeﬁned if overﬂow or divide by

zero occurs.

V — Set if division overﬂow occurs; undeﬁned if divide by zero occurs; cleared oth-

erwise.

C — Always cleared.

XNZVC

—∗∗∗0

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-93

DIVS, DIVSL Signed Divide DIVS, DIVSL

(M68000 Family)

Instruction Format:

WORD

Instruction Fields:

destination operand.

Effective Address ﬁeld—Speciﬁes the source operand. Only data alterable addressing

modes can be used as listed in the following tables:

*Can be used with CPU32.

NOTE

Overﬂow occurs if the quotient is larger than a 16-bit signed

integer.

1514131211109876543210

1000 REGISTER 1 1 1

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-94 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

DIVS, DIVSL Signed Divide DIVS, DIVSL

(M68000 Family)

Instruction Format:

LONG

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the source operand. Only data alterable addressing

modes can be used as listed in the following tables:

32 bits of the dividend comes from this register, and the 32-bit quotient is loaded

into this register.

Size ﬁeld—Selects a 32- or 64-bit division operation.

0 — 32-bit dividend is in register Dq.

1 — 64-bit dividend is in Dr – Dq.

1514131211109876543210

0100110001

EFFECTIVE ADDRESS

MODE REGISTER

0 REGISTER Dq 1 SIZE 0000000 REGISTER Dr

MC68020, MC68030, and MC68040 only

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-95

DIVS, DIVSL Signed Divide DIVS, DIVSL

(M68000 Family)

and Dq are the same register, only the quotient is returned. If the size ﬁeld is 1,

this ﬁeld also speciﬁes the data register that contains the high-order 32 bits of the

dividend.

NOTE

Overﬂow occurs if the quotient is larger than a 32-bit signed

integer.

Integer Instructions

4-96 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

DIVU, DIVUL Unsigned Divide DIVU, DIVUL

(M68000 Family)

Operation: Destination ÷ Source → Destination

Assembler DIVU.W < ea > ,Dn32/16 → 16r – 16q

Syntax: *DIVU.L < ea > ,Dq 32/32 → 32q

*DIVU.L < ea > ,Dr:Dq 64/32 → 32r – 32q

*DIVUL.L < ea > ,Dr:Dq 32/32 → 32r – 32q

*Applies to MC68020, MC68030, MC68040, CPU32 only.

Attributes: Size = (Word, Long)

Description: Divides the unsigned destination operand by the unsigned source

operand and stores the unsigned result in the destination. The instruction uses one of

four forms. The word form of the instruction divides a long word by a word. The result

is a quotient in the lower word (least signiﬁcant 16 bits) and a remainder in the upper

word (most signiﬁcant 16 bits).

The first long form divides a long word by a long word. The result is a long quotient; the

remainder is discarded.

The second long form divides a quad word (in any two data registers) by a long word.

The result is a long-word quotient and a long-word remainder.

The third long form divides a long word by a long word. The result is a long-word quo-

tient and a long-word remainder.

Two special conditions may arise during the operation:

1. Division by zero causes a trap.

2. Overflow may be detected and set before the instruction completes. If the in-

struction detects an overflow, it sets the overflow condition code, and the oper-

ands are unaffected.

Condition Codes:

X — Not affected.

N — Set if the quotient is negative; cleared otherwise; undeﬁned if overﬂow or divide

by zero occurs.

Z — Set if the quotient is zero; cleared otherwise; undeﬁned if overﬂow or divide by

zero occurs.

V — Set if division overﬂow occurs; cleared otherwise; undeﬁned if divide by zero

occurs.

C — Always cleared.

XNZVC

—∗∗∗0

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-97

DIVU, DIVUL Unsigned Divide DIVU, DIVUL

(M68000 Family)

Instruction Format:

WORD

Instruction Fields:

destination operand.

Effective Address ﬁeld—Speciﬁes the source operand. Only data addressing modes

can be used as listed in the following tables:

**Can be used with CPU32.

NOTE

Overﬂow occurs if the quotient is larger than a 16-bit signed

integer.

1514131211109876543210

1000 REGISTER 0 1 1

EFFECTIVE ADDRESS

MODE REGISTER

MC68020, MC68030, and MC68040 only

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-98 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

DIVU, DIVUL Unsigned Divide DIVU, DIVUL

(M68000 Family)

Instruction Format:

LONG

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the source operand. Only data addressing modes

can be used as listed in the following tables:

32 bits of the dividend comes from this register, and the 32-bit quotient is loaded

into this register.

Size ﬁeld—Selects a 32- or 64-bit division operation.

0 — 32-bit dividend is in register Dq.

1 — 64-bit dividend is in Dr – Dq.

1514131211109876543210

0100110001

EFFECTIVE ADDRESS

MODE REGISTER

0 REGISTER Dq 0 SIZE 0000000 REGISTER Dr

MC68020, MC68030, and MC68040 only

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

MC68020, MC68030, and MC68040 only

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-99

DIVU, DIVUL Unsigned Divide DIVU, DIVUL

(M68000 Family)

and Dq are the same register, only the quotient is returned. If the size ﬁeld is 1,

this ﬁeld also speciﬁes the data register that contains the high-order 32 bits of the

dividend.

NOTE

Overﬂow occurs if the quotient is larger than a 32-bit unsigned

integer.

Integer Instructions

4-100 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

EOR Exclusive-OR Logical EOR

(M68000 Family)

Operation: Source ⊕ Destination → Destination

Assembler

Syntax: EOR Dn, < ea >

Attributes: Size = (Byte, Word, Long)

Description: Performs an exclusive-OR operation on the destination operand using the

source operand and stores the result in the destination location. The size of the

operation may be speciﬁed to be byte, word, or long. The source operand must be a

data register. The destination operand is speciﬁed in the effective address ﬁeld.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the result is set; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

WORD

Instruction Fields:

Opmode ﬁeld

XNZVC

—∗∗00

1514131211109876543210

1011 REGISTER OPMODE

EFFECTIVE ADDRESS

MODE REGISTER

Byte Word Long Operation

100 101 110 < ea > ⊕ Dn → < ea >

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-101

EOR Exclusive-OR Logical EOR

(M68000 Family)

Effective Address ﬁeld—Speciﬁes the destination ope data alterable addressing modes

can be used as listed in the following tables:

*Can be used with CPU32.

NOTE

Memory-to-data-register operations are not allowed. Most

assemblers use EORI when the source is immediate data.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-102 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

EORI Exclusive-OR Immediate EORI

(M68000 Family)

Operation: Immediate Data ⊕ Destination → Destination

Assembler

Syntax: EORI # < data > , < ea >

Attributes: Size = (Byte, Word, Long)

Description: Performs an exclusive-OR operation on the destination operand using the

immediate data and the destination operand and stores the result in the destination

location. The size of the operation may be speciﬁed as byte, word, or long. The size of

the immediate data matches the operation size.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the result is set; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—∗∗00

1514131211109876543210

00001010 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

16-BIT WORD DATA 8-BIT BYTE DATA

32-BIT LONG DATA

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-103

EORI Exclusive-OR Immediate EORI

(M68000 Family)

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00— Byte operation

01— Word operation

10— Long operation

Effective Address ﬁeld—Speciﬁes the destination operand. Only data alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

Immediate ﬁeld—Data immediately following the instruction.

If size = 00, the data is the low-order byte of the immediate word.

If size = 01, the data is the entire immediate word.

If size = 10, the data is next two immediate words.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-104 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

EORI EORI

to CCR Exclusive-OR Immediate to CCR

to Condition Code

(M68000 Family)

Operation: Source ⊕ CCR → CCR

Assembler

Syntax: EORI # < data > ,CCR

Attributes: Size = (Byte)

Description: Performs an exclusive-OR operation on the condition code register using the

immediate operand and stores the result in the condition code register (low-order byte

of the status register). All implemented bits of the condition code register are affected.

Condition Codes:

X — Changed if bit 4 of immediate operand is one; unchanged otherwise.

N — Changed if bit 3 of immediate operand is one; unchanged otherwise.

Z — Changed if bit 2 of immediate operand is one; unchanged otherwise.

V — Changed if bit 1 of immediate operand is one; unchanged otherwise.

C — Changed if bit 0 of immediate operand is one; unchanged otherwise.

Instruction Format:

XNZVC

∗∗∗∗∗

1514131211109876543210

0000101000111100

00000000 8-BIT BYTE DATA

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-105

EXG Exchange Registers EXG

(M68000 Family)

Operation: Rx ←→ Ry

Assembler EXG Dx,Dy

Syntax: EXG Ax,Ay EXG Dx,Ay

Attributes: Size = (Long)

Description: Exchanges the contents of two 32-bit registers. The instruction performs three

types of exchanges.

1. Exchange data registers.

2. Exchange address registers.

3. Exchange a data register and an address register.

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

the mode. If the exchange is between data and address registers, this ﬁeld always

speciﬁes the data register.

Opmode ﬁeld—Speciﬁes the type of exchange.

01000—Data registers

01001—Address registers

10001—Data register and address register

the mode. If the exchange is between data and address registers, this ﬁeld always

speciﬁes the address register.

1514131211109876543210

1100 REGISTER Rx 1 OPMODE REGISTER Ry

Integer Instructions

4-106 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

EXT, EXTB Sign-Extend EXT, EXTB

(M68000 Family)

Operation: Destination Sign-Extended → Destination

Assembler EXT.W Dnextend byte to word

Syntax: EXT.L Dnextend word to long word

EXTB.L Dnextend byte to long word (MC68020, MC68030

MC68040, CPU32)

Attributes: Size = (Word, Long)

Description: Extends a byte in a data register to a word or a long word, or a word in a data

byte to a word, bit 7 of the designated data register is copied to bits 15 – 8 of that data

designated register to bits 31 – 8 of the data register.

Condition Codes:

X — Not affected.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

Instruction Fields:

Opmode ﬁeld—Speciﬁes the size of the sign-extension operation.

010—Sign-extend low-order byte of data register to word.

011—Sign-extend low-order word of data register to long.

111— Sign-extend low-order byte of data register to long.

XNZVC

—∗∗00

1514131211109876543210

0100100 OPMODE 0 0 0 REGISTER

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-107

ILLEGAL Take Illegal Instruction Trap ILLEGAL

(M68000 Family)

Operation: *SSP – 2 → SSP; Vector Offset → (SSP);

SSP – 4 → SSP; PC → (SSP);

SSP – 2 → SSP; SR → (SSP);

Illegal Instruction Vector Address → PC

*The MC68000 and MC68008 cannot write the vector offset

and format code to the system stack.

Assembler

Syntax: ILLEGAL

Attributes: Unsized

Description: Forces an illegal instruction exception, vector number 4. All other illegal

instruction bit patterns are reserved for future extension of the instruction set and

should not be used to force an exception.

Condition Codes:

Not affected.

Instruction Format:

1514131211109876543210

0100101011111100

Integer Instructions

4-108 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

JMP Jump JMP

(M68000 Family)

Operation: Destination Address → PC

Assembler

Syntax: JMP < ea >

Attributes: Unsized

Description: Program execution continues at the effective address speciﬁed by the

instruction. The addressing mode for the effective address must be a control

addressing mode.

Condition Codes:

Not affected.

Instruction Format:

Instruction Field:

Effective Address ﬁeld—Speciﬁes the address of the next instruction. Only control

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

1514131211109876543210

0100111011

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-109

JSR Jump to Subroutine JSR

(M68000 Family)

Operation: SP – 4 → Sp; PC → (SP); Destination Address → PC

Assembler

Syntax: JSR < ea >

Attributes: Unsized

Description: Pushes the long-word address of the instruction immediately following the

JSR instruction onto the system stack. Program execution then continues at the

address speciﬁed in the instruction.

Condition Codes:

Not affected.

Instruction Format:

Instruction Field:

Effective Address ﬁeld—Speciﬁes the address of the next instruction. Only control

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

1514131211109876543210

0100111010

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-110 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

LEA Load Effective Address LEA

(M68000 Family)

Operation: < ea > → An

Assembler

Syntax: LEA < ea > ,An

Attributes: Size = (Long)

Description: Loads the effective address into the speciﬁed address register. All 32 bits of

the address register are affected by this instruction.

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the address to be loaded into the address register.

Only control addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

1514131211109876543210

0100 REGISTER 1 1 1

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-111

LINK Link and Allocate LINK

(M68000 Family)

Operation: SP – 4 → SP; An → (SP); SP → An; SP + d

→ SP

Assembler

Syntax: LINK An, # < displacement >

Attributes: Size = (Word, Long*)

*MC68020, MC68030, MC68040 and CPU32 only.

Description: Pushes the contents of the speciﬁed address register onto the stack. Then

loads the updated stack pointer into the address register. Finally, adds the

displacement value to the stack pointer. For word-size operation, the displacement is

the sign-extended word following the operation word. For long size operation, the

displacement is the long word following the operation word. The address register

occupies one long word on the stack. The user should specify a negative displacement

in order to allocate stack area.

Condition Codes:

Not affected.

Instruction Format:

WORD

Instruction Format:

LONG

1514131211109876543210

0100111001010 REGISTER

WORD DISPLACEMENT

1514131211109876543210

0100100000001 REGISTER

HIGH-ORDER DISPLACEMENT

LOW-ORDER DISPLACEMENT

Integer Instructions

4-112 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

LINK Link and Allocate LINK

(M68000 Family)

Instruction Fields:

Displacement ﬁeld—Speciﬁes the twos complement integer to be added to the stack

pointer.

NOTE

LINK and UNLK can be used to maintain a linked list of local data

and parameter areas on the stack for nested subroutine calls.

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-113

LSL, LSR Logical Shift LSL, LSR

(M68000 Family)

Operation: Destination Shifted By Count → Destination

Assembler LSd Dx,Dy

Syntax: LSd # < data > ,Dy

LSd < ea >

where d is direction, L or R

Attributes: Size = (Byte, Word, Long)

Description: Shifts the bits of the operand in the direction speciﬁed (L or R). The carry bit

receives the last bit shifted out of the operand. The shift count for the shifting of a

1. Immediate—The shift count (1 – 8) is specified in the instruction.

2. Register—The shift count is the value in the data register specified in the in-

struction modulo 64.

The size of the operation for register destinations may be specified as byte, word, or

long. The contents of memory, < ea > , can be shifted one bit only, and the operand

size is restricted to a word.

The LSL instruction shifts the operand to the left the number of positions specified as

the shift count. Bits shifted out of the high-order bit go to both the carry and the extend

bits; zeros are shifted into the low-order bit.

The LSR instruction shifts the operand to the right the number of positions specified as

the shift count. Bits shifted out of the low-order bit go to both the carry and the extend

bits; zeros are shifted into the high-order bit.

C OPERAND O

LSL:

O OPERAND C

LSR:

Integer Instructions

4-114 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

LSL, LSR Logical Shift LSL, LSR

(M68000 Family)

Condition Codes:

X — Set according to the last bit shifted out of the operand; unaffected for a shift

count of zero.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Set according to the last bit shifted out of the operand; cleared for a shift count

of zero.

Instruction Format:

Instruction Fields:

Count/Register ﬁeld

If i/r = 0, this ﬁeld contains the shift count. The values 1 – 7 represent shifts of 1 – 7;

value of zero speciﬁes a shift count of eight.

If i/r = 1, the data register speciﬁed in this ﬁeld contains the shift count (modulo 64).

dr ﬁeld—Speciﬁes the direction of the shift.

0 — Shift right

1 — Shift left

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation i/r ﬁeld

If i/r = 0, speciﬁes immediate shift count.

If i/r = 1, speciﬁes register shift count.

XNZVC

∗∗∗0∗

1514131211109876543210

1110

COUNT/

dr SIZE i/r 0 1 REGISTER

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-115

LSL, LSR Logical Shift LSL, LSR

(M68000 Family)

Instruction Format:

MEMORY SHIFTS

Instruction Fields:

dr ﬁeld—Speciﬁes the direction of the shift.

0 — Shift right

1 — Shift left

Effective Address ﬁeld—Speciﬁes the operand to be shifted. Only memory alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

1514131211109876543210

1110001dr11

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-116 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MOVE Move Data from Source to Destination MOVE

(M68000 Family)

Operation: Source → Destination

Assembler

Syntax: MOVE < ea > , < ea >

Attributes: Size = (Byte, Word, Long)

Description: Moves the data at the source to the destination location and sets the condition

codes according to the data. The size of the operation may be speciﬁed as byte, word,

or long. Condition Codes:

X — Not affected.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operand to be moved.

01 — Byte operation

11 — Word operation

10 — Long operation

XNZVC

—∗∗00

1514131211109876543210

0 0 SIZE

DESTINATION SOURCE

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-117

MOVE Move Data from Source to Destination MOVE

(M68000 Family)

Destination Effective Address ﬁeld—Speciﬁes the destination location. Only data

alterable addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-118 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MOVE Move Data from Source to Destination MOVE

(M68000 Family)

Source Effective Address ﬁeld—Speciﬁes the source operand. All addressing modes

can be used as listed in the following tables:

*For byte size operation, address register direct is not allowed.

**Can be used with CPU32.

NOTE

Most assemblers use MOVEA when the destination is an

address register.

MOVEQ can be used to move an immediate 8-bit value to a data

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)** 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-119

MOVEA Move Address MOVEA

(M68000 Family)

Operation: Source → Destination

Assembler

Syntax: MOVEA < ea > ,An

Attributes: Size = (Word, Long)

Description: Moves the contents of the source to the destination address register. The size

of the operation is speciﬁed as word or long. Word-size source operands are sign-

extended to 32-bit quantities.

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operand to be moved.

11 — Word operation; the source operand is sign-extended to a long operand and

all 32 bits are loaded into the address register.

10 — Long operation.

Destination Register ﬁeld—Speciﬁes the destination address register.

1514131211109876543210

0 0 SIZE

DESTINATION

001

SOURCE

MODE REGISTER

Integer Instructions

4-120 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MOVEA Move Address MOVEA

(M68000 Family)

Effective Address ﬁeld—Speciﬁes the location of the source operand. All addressing

modes can be used as listed in the following tables:

*Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-121

MOVE MOVE

from CCR Move from the from CCR

Condition Code Register

(MC68010, MC68020, MC68030, MC68040, CPU32)

Operation: CCR → Destination

Assembler

Syntax: MOVE CCR, < ea >

Attributes: Size = (Word)

Description: Moves the condition code bits (zero-extended to word size) to the destination

location. The operand size is a word. Unimplemented bits are read as zeros.

Condition Codes:

Not affected.

Instruction Format:

1514131211109876543210

0100001011

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

4-122 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MOVE MOVE

from CCR Move from the from CCR

Condition Code Register

(MC68010, MC68020, MC68030, MC68040, CPU32)

Instruction Field:

Effective Address ﬁeld—Speciﬁes the destination location. Only data alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

NOTE

MOVE from CCR is a word operation. ANDI, ORI, and EORI to

CCR are byte operations.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-123

MOVE MOVE

to CCR Move to Condition Code Register to CCR

(M68000 Family)

Operation: Source → CCR

Assembler

Syntax: MOVE < ea > ,CCR

Attributes: Size = (Word)

Description: Moves the low-order byte of the source operand to the condition code register.

The upper byte of the source operand is ignored; the upper byte of the status register

is not altered.

Condition Codes:

X — Set to the value of bit 4 of the source operand.

N — Set to the value of bit 3 of the source operand.

Z — Set to the value of bit 2 of the source operand.

V — Set to the value of bit 1 of the source operand.

C — Set to the value of bit 0 of the source operand.

Instruction Format:

XNZVC

∗∗∗∗∗

1514131211109876543210

0100010011

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

4-124 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MOVE MOVE

to CCR Move to Condition Code Register to CCR

(M68000 Family)

Instruction Field:

Effective Address ﬁeld—Speciﬁes the location of the source operand. Only data

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

NOTE

MOVE to CCR is a word operation. ANDI, ORI, and EORI to

CCR are byte operations.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-125

MOVE MOVE

from SR Move from the Status Register from SR

(MC68000, MC68008)

Operation: SR → Destination

Assembler

Syntax: MOVE SR, < ea >

Attributes: Size = (Word)

Description: Moves the data in the status register to the destination location. The

destination is word length. Unimplemented bits are read as zeros.

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the destination location. Only data alterable

addressing modes can be used as listed in the following table:

NOTE

Use the MOVE from CCR instruction to access only the

condition codes. Memory destination is read before it is written

to.

1514131211109876543210

0100000011

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

Integer Instructions

4-126 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MOVE16 Move 16-Byte Block MOVE16

(MC68040)

Operation: Source Block → Destination Block

Assembler MOVE16 (Ax) + ,(Ay) +

Syntax: MOVE16 (xxx).L,(An)

MOVE16 (xxx).L,(An) +

MOVE16 (An),(xxx).L

MOVE16 (An) + ,(xxx).L

Attributes: Size = (Line)

Description: Moves the source line to the destination line. The lines are aligned to 16-byte

boundaries. Applications for this instruction include coprocessor communications,

memory initialization, and fast block copy operations.

MOVE16 has two formats. The postincrement format uses the postincrement address-

ing mode for both source and destination; whereas, the absolute format specifies an

absolute long address for either the source or destination.

Line transfers are performed using burst reads and writes, which begin with the long

word pointed to by the effective address of the source and destination, respectively. An

address register used in the postincrement addressing mode is incremented by 16

after the transfer.

Example: MOVE16 (A0) + $FE802 A0 = $1400F

The line at address $14000 is read into a temporary holding register by a burst read

transfer starting with long-word $14000. Address values in A0 of $14000 – $1400F

cause the same line to be read, starting at different long words. The line is then written

to the line at address $FE800 beginning with long-word $FE800 after the instruction A0

contains $1401F.

Source line at $14000:

Destination line at $FE8000:

$14000 $14004 $14008 $1400C

LONG WORD 0 LONG WORD 1 LONG WORD 2 LONG WORD 3

$FE800 $FE804 $FE808 $FE80C

LONG WORD 0 LONG WORD 1 LONG WORD 2 LONG WORD 3

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-127

MOVE16 Move 16-Byte Block MOVE16

(MC68040)

Condition Codes:

Not affected.

Instruction Format:

POSTINCREMENT SOURCE AND DESTINATION

Instruction Fields:

mode.

addressing mode.

Instruction Format:

Absolute Long Address Source or Destination

Instruction Fields:

Opmode ﬁeld—Speciﬁes the addressing modes used for source and destination:

addressing mode used as a source or destination.

32-Bit Address ﬁeld—Speciﬁes the absolute address used as a source or destination.

1514131211109876543210

1111011000100 REGISTER Ax

1 REGISTER Ay 000000000000

1514131211109876543210

11110110000OPMODE REGISTER Ay

HIGH-ORDER ADDRESS

LOW-ORDER ADDRESS

Opmode Source Destinati on Assembler Syntax

0 0 (Ay) + (xxx).L MOVE16 (Ay) + ,(xxx).L

0 1 (xxx).L (Ay) + MOVE16 (xxx).L,(Ay) +

1 0 (Ay) (xxx).L MOVE16 (Ay),(xxx).L

1 1 (xxx).L (Ay) MOVE16 (xxx).L,(Ay)

Integer Instructions

4-128 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MOVEM Move Multiple Registers MOVEM

(M68000 Family)

Operation: Registers → Destination; Source → Registers

Assembler MOVEM < list > , < ea >

Syntax: MOVEM < ea > , < list >

Attributes: Size = (Word, Long)

Description: Moves the contents of selected registers to or from consecutive memory

locations starting at the location speciﬁed by the effective address. A register is

selected if the bit in the mask ﬁeld corresponding to that register is set. The instruction

size determines whether 16 or 32 bits of each register are transferred. In the case of a

word transfer to either address or data registers, each word is sign-extended to 32 bits,

and the resulting long word is loaded into the associated register.

Selecting the addressing mode also selects the mode of operation of the MOVEM

instruction, and only the control modes, the predecrement mode, and the postincre-

ment mode are valid. If the effective address is specified by one of the control modes,

the registers are transferred starting at the specified address, and the address is incre-

mented by the operand length (2 or 4) following each transfer. The order of the regis-

ters is from D0 to D7, then from A0 to A7.

If the effective address is specified by the predecrement mode, only a register-to-mem-

ory operation is allowed. The registers are stored starting at the specified address

minus the operand length (2 or 4), and the address is decremented by the operand

length following each transfer. The order of storing is from A7 to A0, then from D7 to

D0. When the instruction has completed, the decremented address register contains

the address of the last operand stored. For the MC68020, MC68030, MC68040, and

CPU32, if the addressing register is also moved to memory, the value written is the ini-

tial register value decremented by the size of the operation. The MC68000 and

MC68010 write the initial register value (not decremented).

If the effective address is specified by the postincrement mode, only a memory-to-reg-

ister operation is allowed. The registers are loaded starting at the specified address;

the address is incremented by the operand length (2 or 4) following each transfer. The

order of loading is the same as that of control mode addressing. When the instruction

has completed, the incremented address register contains the address of the last oper-

and loaded plus the operand length. If the addressing register is also loaded from

memory, the memory value is ignored and the register is written with the postincre-

mented effective address.

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-129

MOVEM Move Multiple Registers MOVEM

(M68000 Family)

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

dr ﬁeld—Speciﬁes the direction of the transfer.

0 — Register to memory.

1 — Memory to register.

Size ﬁeld—Speciﬁes the size of the registers being transferred.

0 — Word transfer

1 — Long transfer

Effective Address ﬁeld—Speciﬁes the memory address for the operation. For register-

to-memory transfers, only control alterable addressing modes or the

predecrement addressing mode can be used as listed in the following tables:

*Can be used with CPU32.

1514131211109876543210

01001dr001SIZE

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-130 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MOVEM Move Multiple Registers MOVEM

(M68000 Family)

For memory-to-register transfers, only control addressing modes or the postincrement

addressing mode can be used as listed in the following tables:

*Can be used with CPU32.

corresponds to the ﬁrst register to be transferred; the high-order bit corresponds

to the last register to be transferred. Thus, for both control modes and

postincrement mode addresses, the mask correspondence is:

For the predecrement mode addresses, the mask correspondence is reversed:

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) — —

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

1514131211109876543210

A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

1514131211109876543210

D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-131

MOVEP Move Peripheral Data MOVEP

(M68000 Family)

Operation: Source → Destination

Assembler MOVEP Dx,(d16

,Ay)

Syntax: MOVEP (d16

,Ay),Dx

Attributes: Size = (Word, Long)

Description: Moves data between a data register and alternate bytes within the address

space starting at the location speciﬁed and incrementing by two. The high-order byte

of the data register is transferred ﬁrst, and the low-order byte is transferred last. The

memory address is speciﬁed in the address register indirect plus 16-bit displacement

addressing mode. This instruction was originally designed for interfacing 8-bit

peripherals on a 16-bit data bus, such as the MC68000 bus. Although supported by the

MC68020, MC68030, and MC68040, this instruction is not useful for those processors

with an external 32-bit bus.

Example: Long transfer to/from an even address.

Byte Organization in Register

Byte Organization in

16-Bit Memory

(Low Address at Top)

31 24 23 16 15 8 7 0

HIGH ORDER MID UPPER MID LOWER LOW ORDER

15 8 7 0

HIGH ORDER

MID UPPER

MID LOWER

LOW ORDER

Integer Instructions

4-132 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MOVEP Move Peripheral Data MOVEP

(M68000 Family)

Byte Organization in 32-Bit Memory

Example:Word transfer to/from (odd address).

Byte Organization in Register

Byte Organization in

16-Bit Memory

(Low Address at Top)

Byte Organization in 32-Bit Memory

31 24 23 16 15 8 7 0

HIGH ORDER MID UPPER

MID LOWER LOW ORDER

31 24 23 16 15 8 7 0

HIGH ORDER

MID UPPER MID LOWER

LOW ORDER

31 24 23 16 15 8 7 0

HIGH ORDER LOW ORDER

15 8 7 0

HIGH ORDER

LOW ORDER

31 24 23 16 15 8 7 0

HIGH ORDER

LOW ORDER

31 24 23 16 15 8 7 0

HIGH ORDER LOW ORDER

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-133

MOVEP Move Peripheral Data MOVEP

(M68000 Family)

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

Data Register ﬁeld—Speciﬁes the data register for the instruction.

Opmode ﬁeld—Speciﬁes the direction and size of the operation.

100—Transfer word from memory to register.

101—Transfer long from memory to register.

110—Transfer word from register to memory.

111— Transfer long from register to memory.

Address Register ﬁeld—Speciﬁes the address register which is used in the address

Displacement ﬁeld—Speciﬁes the displacement used in the operand address.

1514131211109876543210

0000DATA REGISTER OPMODE 0 0 1 ADDRESS REGISTER

16-BIT DISPLACEMENT

Integer Instructions

4-134 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MOVEQ Move Quick MOVEQ

(M68000 Family)

Operation: Immediate Data → Destination

Assembler

Syntax: MOVEQ # < data > ,Dn

Attributes: Size = (Long)

Description: Moves a byte of immediate data to a 32-bit data register. The data in an 8-bit

ﬁeld within the operation word is sign- extended to a long operand in the data register

as it is transferred.

Condition Codes:

X — Not affected.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

Instruction Fields:

Data ﬁeld—Eight bits of data, which are sign-extended to a long operand.

XNZVC

—∗∗00

1514131211109876543210

0111 REGISTER 0 DATA

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-135

MULS Signed Multiply MULS

(M68000 Family)

Operation: Source x Destination → Destination

Assembler MULS.W < ea > ,Dn16 x 16 → 32

Syntax: *MULS.L < ea > ,Dl 32 x 32 → 32

*MULS.L < ea > ,Dh – Dl 32 x 32 → 64

*Applies to MC68020, MC68030, MC68040, CPU32

Attributes: Size = (Word, Long)

Description: Multiplies two signed operands yielding a signed result. This instruction has a

word operand form and a long operand form.

In the word form, the multiplier and multiplicand are both word operands, and the result

is a long-word operand. A register operand is the low-order word; the upper word of the

In the long form, the multiplier and multiplicand are both long- word operands, and the

result is either a long word or a quad word. The long-word result is the low-order 32 bits

of the quad- word result; the high-order 32 bits of the product are discarded.

Condition Codes:

X — Not affected.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if overﬂow; cleared otherwise.

C — Always cleared.

NOTE

Overﬂow (V = 1) can occur only when multiplying 32-bit

operands to yield a 32-bit result. Overﬂow occurs if the high-

order 32 bits of the quad-word product are not the sign extension

of the low- order 32 bits.

XNZVC

—∗∗∗0

Integer Instructions

4-136 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MULS Signed Multiply MULS

(M68000 Family)

Instruction Format:

WORD

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the source operand. Only data alterable addressing

modes can be used as listed in the following tables:

*Can be used with CPU32.

1514131211109876543210

1100 REGISTER 1 1 1

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-137

MULS Signed Multiply MULS

(M68000 Family)

Instruction Format:

LONG

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the source operand. Only data addressing modes

can be used as listed in the following tables:

*Can be used with CPU32.

multiplicand comes from this register, and the low-order 32 bits of the product are

loaded into this register.

Size ﬁeld—Selects a 32- or 64-bit product.

0 — 32-bit product to be returned to register Dl.

1 — 64-bit product to be returned to Dh – Dl.

32 bits of the product are loaded. If Dh = Dl and size is one, the results of the

operation are undeﬁned. Otherwise, this ﬁeld is unused.

1514131211109876543210

0100110000

EFFECTIVE ADDRESS

MODE REGISTER

0 REGISTER DI 1 SIZE 0000000 REGISTER Dh

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-138 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MULU Unsigned Multiply MULU

(M68000 Family)

Operation: Source x Destination → Destination

Assembler MULU.W < ea > ,Dn16 x 16 → 32

Syntax: *MULU.L < ea > ,Dl 32 x 32 → 32

*MULU.L < ea > ,Dh – Dl 32 x 32 → 64

*Applies to MC68020, MC68030, MC68040, CPU32 only

Attributes: Size = (Word, Long)

Description: Multiplies two unsigned operands yielding an unsigned result. This instruction

has a word operand form and a long operand form.

In the word form, the multiplier and multiplicand are both word operands, and the result

is a long-word operand. A register operand is the low-order word; the upper word of the

In the long form, the multiplier and multiplicand are both long- word operands, and the

result is either a long word or a quad word. The long-word result is the low-order 32 bits

of the quad- word result; the high-order 32 bits of the product are discarded.

Condition Codes:

X — Not affected.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if overﬂow; cleared otherwise.

C — Always cleared.

NOTE

Overﬂow (V = 1) can occur only when multiplying 32-bit

operands to yield a 32-bit result. Overﬂow occurs if any of the

high-order 32 bits of the quad-word product are not equal to

zero.

XNZVC

—∗∗∗0

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-139

MULU Unsigned Multiply MULU

(M68000 Family)

Instruction Format:

WORD

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the source operand. Only data addressing modes

can be used as listed in the following tables:

*Can be used with CPU32.

1514131211109876543210

1100 REGISTER 0 1 1

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-140 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MULU Unsigned Multiply MULU

(M68000 Family)

Instruction Format:

LONG

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the source operand. Only data addressing modes

can be used as listed in the following tables:

*Can be used with CPU32.

multiplicand comes from this register, and the low-order 32 bits of the product are

loaded into this register.

Size ﬁeld—Selects a 32- or 64-bit product.

0 — 32-bit product to be returned to register Dl.

1 — 64-bit product to be returned to Dh – Dl.

32 bits of the product are loaded. If Dh = Dl and size is one, the results of the

operation are undeﬁned. Otherwise, this ﬁeld is unused.

1514131211109876543210

0100110000

EFFECTIVE ADDRESS

MODE REGISTER

0 REGISTER Dl 0 SIZE 0000000 REGISTER Dh

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-141

NBCD Negate Decimal with Extend NBCD

(M68000 Family)

Operation: 0 – Destination

– X → Destination

Assembler

Syntax: NBCD < ea >

Attributes: Size = (Byte)

Description: Subtracts the destination operand and the extend bit from zero. The operation

is performed using binary-coded decimal arithmetic. The packed binary-coded decimal

result is saved in the destination location. This instruction produces the tens

complement of the destination if the extend bit is zero or the nines complement if the

extend bit is one. This is a byte operation only.

Condition Codes:

X — Set the same as the carry bit.

N — Undeﬁned.

Z — Cleared if the result is nonzero; unchanged otherwise.

V — Undeﬁned.

C — Set if a decimal borrow occurs; cleared otherwise.

NOTE

Normally the Z condition code bit is set via programming before

the start of the operation. This allows successful tests for zero

results upon completion of multiple-precision operations.

XNZVC

∗U∗U∗

Integer Instructions

4-142 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

NBCD Negate Decimal with Extend NBCD

(M68000 Family)

Instruction Format:

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the destination operand. Only data alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

1514131211109876543210

0100100000

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-143

NEG Negate NEG

(M68000 Family)

Operation: 0 – Destination → Destination

Assembler

Syntax: NEG < ea >

Attributes: Size = (Byte, Word, Long)

Description: Subtracts the destination operand from zero and stores the result in the

destination location. The size of the operation is speciﬁed as byte, word, or long.

Condition Codes:

X — Set the same as the carry bit.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if an overﬂow occurs; cleared otherwise.

C — Cleared if the result is zero; set otherwise.

Instruction Format:

XNZVC

∗∗∗∗∗

1514131211109876543210

01000100 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

4-144 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

NEG Negate NEG

(M68000 Family)

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

Effective Address ﬁeld—Speciﬁes the destination operand. Only data alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn) 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-145

NEGX Negate with Extend NEGX

(M68000 Family)

Operation: 0 – Destination – X → Destination

Assembler

Syntax: NEGX < ea >

Attributes: Size = (Byte, Word, Long)

Description: Subtracts the destination operand and the extend bit from zero. Stores the

result in the destination location. The size of the operation is speciﬁed as byte, word,

or long.

Condition Codes:

X — Set the same as the carry bit.

N — Set if the result is negative; cleared otherwise.

Z — Cleared if the result is nonzero; unchanged otherwise.

V — Set if an overﬂow occurs; cleared otherwise.

C — Set if a borrow occurs; cleared otherwise.

NOTE

Normally the Z condition code bit is set via programming before

the start of the operation. This allows successful tests for zero

results upon completion of multiple-precision operations.

XNZVC

∗∗∗∗∗

Integer Instructions

4-146 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

NEGX Negate with Extend NEGX

(M68000 Family)

Instruction Format:

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

Effective Address ﬁeld—Speciﬁes the destination operand. Only data alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

1514131211109876543210

01000000 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-147

NOP No Operation NOP

(M68000 Family)

Operation: None

Assembler

Syntax: NOP

Attributes: Unsized

Description: Performs no operation. The processor state, other than the program counter,

is unaffected. Execution continues with the instruction following the NOP instruction.

The NOP instruction does not begin execution until all pending bus cycles have

completed. This synchronizes the pipeline and prevents instruction overlap.

Condition Codes:

Not affected.

Instruction Format:

1514131211109876543210

0100111001110001

Integer Instructions

4-148 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

NOT Logical Complement NOT

(M68000 Family)

Operation: ~ Destination → Destination

Assembler

Syntax: NOT < ea >

Attributes: Size = (Byte, Word, Long)

Description:Calculates the ones complement of the destination operand and stores the

result in the destination location. The size of the operation is speciﬁed as byte, word,

or long.

Condition Codes:

X — Not affected.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—∗∗00

1514131211109876543210

01000110 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-149

NOT Logical Complement NOT

(M68000 Family)

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00— Byte operation

01— Word operation

10— Long operation

Effective Address ﬁeld—Speciﬁes the destination operand. Only data alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-150 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

OR Inclusive-OR Logical OR

(M68000 Family)

Operation: Source V Destination → Destination

Assembler OR < ea > ,Dn

Syntax: OR Dn, < ea >

Attributes: Size = (Byte, Word, Long)

Description: Performs an inclusive-OR operation on the source operand and the

destination operand and stores the result in the destination location. The size of the

operation is speciﬁed as byte, word, or long. The contents of an address register may

not be used as an operand.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the result is set; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

Instruction Fields:

Opmode ﬁeld

XNZVC

—∗∗00

1514131211109876543210

1000 REGISTER OPMODE

EFFECTIVE ADDRESS

MODE REGISTER

Byte Word Long Operation

000 001 010 < ea > V Dn → Dn

100 101 110 Dn V < ea > → < ea >

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-151

OR Inclusive-OR Logical OR

(M68000 Family)

Effective Address ﬁeld—If the location speciﬁed is a source operand, only data

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-152 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

OR Inclusive-OR Logical OR

(M68000 Family)

If the location speciﬁed is a destination operand, only memory alterable addressing

modes can be used as listed in the following tables:

*Can be used with CPU32.

NOTE

If the destination is a data register, it must be speciﬁed using the

destination Dn mode, not the destination < ea > mode.

Most assemblers use ORI when the source is immediate data.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-153

ORI Inclusive-OR ORI

(M68000 Family)

Operation: Immediate Data V Destination → Destination

Assembler

Syntax: ORI # < data > , < ea >

Attributes: Size = (Byte, Word, Long)

Description: Performs an inclusive-OR operation on the immediate data and the

destination operand and stores the result in the destination location. The size of the

operation is speciﬁed as byte, word, or long. The size of the immediate data matches

the operation size.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the result is set; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—∗∗00

1514131211109876543210

00000000 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

16-BIT WORD DATA 8-BIT BYTE DATA

32-BIT LONG DATA

Integer Instructions

4-154 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

ORI Inclusive-OR ORI

(M68000 Family)

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00— Byte operation

01— Word operation

10— Long operation

Effective Address ﬁeld—Speciﬁes the destination operand. Only data alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

Immediate ﬁeld—Data immediately following the instruction.

If size = 00, the data is the low-order byte of the immediate word.

If size = 01, the data is the entire immediate word.

If size = 10, the data is the next two immediate words.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-155

ORI ORI

to CCR Inclusive-OR Immediate to CCR

to Condition Codes

(M68000 Family)

Operation: Source V CCR → CCR

Assembler

Syntax: ORI # < data > ,CCR

Attributes: Size = (Byte)

Description: Performs an inclusive-OR operation on the immediate operand and the

condition codes and stores the result in the condition code register (low-order byte of

the status register). All implemented bits of the condition code register are affected.

Condition Codes:

X — Set if bit 4 of immediate operand is one; unchanged otherwise.

N — Set if bit 3 of immediate operand is one; unchanged otherwise.

Z — Set if bit 2 of immediate operand is one; unchanged otherwise.

V — Set if bit 1 of immediate operand is one; unchanged otherwise.

C — Set if bit 0 of immediate operand is one; unchanged otherwise.

Instruction Format:

XNZVC

∗∗∗∗∗

1514131211109876543210

0000000000111100

00000000 8-BIT BYTE DATA

Integer Instructions

4-156 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

PACK Pack PACK

(MC68020, MC68030, MC68040)

Operation: Source (Unpacked BCD) + Adjustment → Destination (Packed BCD)

Assembler PACK – (Ax), – (Ay),# < adjustment >

Syntax: PACK Dx,Dy,# < adjustment >

Attributes: Unsized

Description: Adjusts and packs the lower four bits of each of two bytes into a single byte.

When both operands are data registers, the adjustment is added to the value contained

in the source register. Bits 11 – 8 and 3 – 0 of the intermediate result are concatenated

and placed in bits 7 – 0 of the destination register. The remainder of the destination

Source:

Add Adjustment Word:

Resulting in:

Destination:

When the predecrement addressing mode is specified, two bytes from the source are

fetched and concatenated. The adjustment word is added to the concatenated bytes.

Bits 3 – 0 of each byte are extracted. These eight bits are concatenated to form a new

byte which is then written to the destination.

1514131211109876543210

xxxxabcdxxxxefgh

15 0

16-BIT EXTENSION

1514131211109876543210

x’ x’ x’ x’ a’ b’ c’ d’ x’ x’ x’ x’ e’ f’ g’ h’

1514131211109876543210

uuuuuuuua’b’c’d’e’f’g’h’

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-157

PACK Pack PACK

(MC68020, MC68030, MC68040)

Source:

Concatenated Word:

Add Adjustment Word:

Destination:

Condition Codes:

Not affected.

Instruction Format:

76543210

xxxxabcd

xxxxefgh

1514131211109876543210

xxxxabcdxxxxefgh

15 0

16-BIT EXTENSION

76543210

a’ b’ c’ d’ e’ f’ g’ h’

1514131211109876543210

1000REGISTER Dy/Ay 10100R/MREGISTER Dx/Ax

16-BIT ADJUSTMENT EXTENSION:

Integer Instructions

4-158 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

PACK Pack PACK

(MC68020, MC68030, MC68040)

Instruction Fields:

If R/M = 0, speciﬁes a data register.

If R/M = 1, speciﬁes an address register in the predecrement addressing mode.

R/M ﬁeld—Speciﬁes the operand addressing mode.

0 — The operation is data register to data register.

1 — The operation is memory to memory.

If R/M = 0, speciﬁes a data register.

If R/M = 1, speciﬁes an address register in the predecrement addressing mode.

Adjustment ﬁeld—Immediate data word that is added to the source operand. This word

is zero to pack ASCII or EBCDIC codes. Other values can be used for other

codes.

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-159

PEA Push Effective Address PEA

(M68000 Family)

Operation: SP – 4 → SP; < ea > → (SP)

Assembler

Syntax: PEA < ea >

Attributes: Size = (Long)

Description: Computes the effective address and pushes it onto the stack. The effective

address is a long address.

Condition Codes:

Not affected.

Instruction Format:

Instruction Field:

Effective Address ﬁeld—Speciﬁes the address to be pushed onto the stack. Only

control addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

1514131211109876543210

0100100001

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-160 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

ROL, ROR Rotate (Without Extend) ROL, ROR

(M68000 Family)

Operation: Destination Rotated By < count > → Destination

Assembler ROd Dx,Dy

Syntax: ROd # < data > ,Dy ROd < ea > where d is direction, L or R

Attributes: Size = (Byte, Word, Long)

Description: Rotates the bits of the operand in the direction speciﬁed (L or R). The extend

bit is not included in the rotation. The rotate count for the rotation of a register is

speciﬁed in either of two ways:

1. Immediate—The rotate count (1 – 8) is specified in the instruction.

2. Register—The rotate count is the value in the data register specified in the in-

struction, modulo 64.

The size of the operation for register destinations is specified as byte, word, or long.

The contents of memory, (ROd < ea > ), can be rotated one bit only, and operand size

is restricted to a word.

The ROL instruction rotates the bits of the operand to the left; the rotate count deter-

mines the number of bit positions rotated. Bits rotated out of the high-order bit go to the

carry bit and also back into the low-order bit.

The ROR instruction rotates the bits of the operand to the right; the rotate count deter-

mines the number of bit positions rotated. Bits rotated out of the low-order bit go to the

carry bit and also back into the high-order bit.

OPERAND

ROL:

OPERAND C

ROR:

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-161

ROL,ROR Rotate (Without Extend) ROL,ROR

(M68000 Family)

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the result is set; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Set according to the last bit rotated out of the operand; cleared when the rotate

count is zero.

Instruction Format:

Instruction Fields:

Count/Register ﬁeld:

If i/r = 0, this ﬁeld contains the rotate count. The values 1 – 7 represent counts of 1

– 7, and zero speciﬁes a count of eight.

If i/r = 1, this ﬁeld speciﬁes a data register that contains the rotate count (modulo 64).

dr ﬁeld—Speciﬁes the direction of the rotate.

0 — Rotate right

1 — Rotate left

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

i/r ﬁeld—Speciﬁes the rotate count location.

If i/r = 0, immediate rotate count.

If i/r = 1, register rotate count.

XNZVC

—∗∗0∗

1514131211109876543210

1110

COUNT/

dr SIZE i/r 1 1 REGISTER

Integer Instructions

4-162 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

ROL, ROR Rotate (Without Extend) ROL, ROR

(M68000 Family)

Instruction Format:

MEMORY ROTATE

Instruction Fields:

dr ﬁeld—Speciﬁes the direction of the rotate.

0 — Rotate right

1 — Rotate left

Effective Address ﬁeld—Speciﬁes the operand to be rotated. Only memory alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

1514131211109876543210

1110011dr11

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-163

ROXL, ROXR Rotate with Extend ROXL, ROXR

(M68000 Family)

Operation: Destination Rotated With X By Count → Destination

Assembler ROXd Dx,Dy

Syntax: ROXd # < data > ,Dy

ROXd < ea >

where d is direction, L or R

Attributes: Size = (Byte, Word, Long)

Description: Rotates the bits of the operand in the direction speciﬁed (L or R). The extend

bit is included in the rotation. The rotate count for the rotation of a register is speciﬁed

in either of two ways:

1. Immediate—The rotate count (1 – 8) is specified in the instruction.

2. Register—The rotate count is the value in the data register specified in the in-

struction, modulo 64.

The size of the operation for register destinations is specified as byte, word, or long.

The contents of memory, < ea > , can be rotated one bit only, and operand size is

restricted to a word. The ROXL instruction rotates the bits of the operand to the left; the

rotate count determines the number of bit positions rotated. Bits rotated out of the high-

order bit go to the carry bit and the extend bit; the previous value of the extend bit

rotates into the low-order bit.

The ROXR instruction rotates the bits of the operand to the right; the rotate count deter-

mines the number of bit positions rotated. Bits rotated out of the low-order bit go to the

carry bit and the extend bit; the previous value of the extend bit rotates into the high-

order bit.

C OPERAND

ROXL:

X OPERAND CROXR:

Integer Instructions

4-164 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

ROXL, ROXR Rotate with Extend ROXL, ROXR

(M68000 Family)

Condition Codes:

X — Set to the value of the last bit rotated out of the operand; unaffected when the

rotate count is zero.

N — Set if the most signiﬁcant bit of the result is set; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Always cleared.

C — Set according to the last bit rotated out of the operand; when the rotate count is

zero, set to the value of the extend bit.

Instruction Format:

Instruction Fields:

Count/Register ﬁeld:

If i/r = 0, this ﬁeld contains the rotate count. The values 1 – 7 represent counts of 1

– 7, and zero speciﬁes a count of eight.

If i/r = 1, this ﬁeld speciﬁes a data register that contains the rotate count (modulo 64).

dr ﬁeld—Speciﬁes the direction of the rotate.

0 — Rotate right

1 — Rotate left

XNZVC

∗∗∗0∗

1514131211109876543210

1110

COUNT/

dr SIZE i/r 1 0 REGISTER

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-165

ROXL, ROXR Rotate with Extend ROXL, ROXR

(M68000 Family)

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

i/r ﬁeld—Speciﬁes the rotate count location.

If i/r = 0, immediate rotate count.

If i/r = 1, register rotate count.

Instruction Format:

MEMORY ROTATE

Instruction Fields:

dr ﬁeld—Speciﬁes the direction of the rotate.

0 — Rotate right

1 — Rotate left

Effective Address ﬁeld—Speciﬁes the operand to be rotated. Only memory alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

1514131211109876543210

1110010dr11

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-166 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

RTD Return and Deallocate RTD

(MC68010, MC68020, MC68030, MC68040, CPU32)

Operation: (SP) → PC; SP + 4 + d

→ SP

Assembler

Syntax: RTD # < displacement >

Attributes: Unsized

Description: Pulls the program counter value from the stack and adds the sign-extended

16-bit displacement value to the stack pointer. The previous program counter value is

lost.

Condition Codes:

Not affected.

Instruction Format:

Instruction Field:

Displacement ﬁeld—Speciﬁes the twos complement integer to be sign-extended and

added to the stack pointer.

1514131211109876543210

0100111001110100

16-BIT DISPLACEMENT

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-167

RTM Return from Module RTM

(MC68020)

Operation: Reload Saved Module State from Stack

Assembler

Syntax: RTM Rn

Attributes: Unsized

Description: A previously saved module state is reloaded from the top of stack. After the

module state is retrieved from the top of the stack, the caller’s stack pointer is

incremented by the argument count value in the module state.

Condition Codes:

Set according to the content of the word on the stack.

Instruction Format:

Instruction Fields:

D/A ﬁeld—Speciﬁes whether the module data pointer is in a data or an address register.

0 — the register is a data register

1 — the register is an address register

restored from the saved module state. If the register speciﬁed is A7 (SP), the

updated value of the register reﬂects the stack pointer operations, and the saved

module data area pointer is lost.

1514131211109876543210

000001101100D/A REGISTER

Integer Instructions

4-168 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

RTR Return and Restore Condition Codes RTR

(M68000 Family)

Operation: (SP) → CCR; SP + 2 → SP; (SP) → PC; SP + 4 → SP

Assembler

Syntax: RTR

Attributes: Unsized

Description: Pulls the condition code and program counter values from the stack. The

previous condition code and program counter values are lost. The supervisor portion

of the status register is unaffected.

Condition Codes:

Set to the condition codes from the stack.

Instruction Format:

1514131211109876543210

0100111001110111

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-169

RTS Return from Subroutine RTS

(M68000 Family)

Operation: (SP) → PC; SP + 4 → SP

Assembler

Syntax: RTS

Attributes: Unsized

Description: Pulls the program counter value from the stack. The previous program counter

value is lost.

Condition Codes:

Not affected.

Instruction Format:

1514131211109876543210

0100111001110101

Integer Instructions

4-170 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

SBCD Subtract Decimal with Extend SBCD

(M68000 Family)

Operation: Destination10 – Source10 – X → Destination

Assembler SBCD Dx,Dy

Syntax: SBCD – (Ax), – (Ay)

Attributes: Size = (Byte)

Description: Subtracts the source operand and the extend bit from the destination operand

and stores the result in the destination location. The subtraction is performed using

binary-coded decimal arithmetic; the operands are packed binary-coded decimal

numbers. The instruction has two modes:

1. Data register to data register—the data registers specified in the instruction con-

tain the operands.

2. Memory to memory—the address registers specified in the instruction access

the operands from memory using the predecrement addressing mode.

This operation is a byte operation only.

Condition Codes:

X — Set the same as the carry bit.

N — Undeﬁned.

Z — Cleared if the result is nonzero; unchanged otherwise.

V — Undeﬁned.

C — Set if a borrow (decimal) is generated; cleared otherwise.

NOTE

Normally the Z condition code bit is set via programming before

the start of an operation. This allows successful tests for zero

results upon completion of multiple-precision operations.

XNZVC

∗U∗U∗

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-171

SBCD Subtract Decimal with Extend SBCD

(M68000 Family)

Instruction Format:

Instruction Fields:

If R/M = 0, speciﬁes a data register.

If R/M = 1, speciﬁes an address register for the predecrement addressing mode.

R/M ﬁeld—Speciﬁes the operand addressing mode.

0 — The operation is data register to data register.

1 — The operation is memory to memory.

If R/M = 0, speciﬁes a data register.

If R/M = 1, speciﬁes an address register for the predecrement addressing mode.

1514131211109876543210

1000REGISTER Dy/Ay 10000R/MREGISTER Dx/Ax

Integer Instructions

4-172 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

Scc Set According to Condition Scc

(M68000 Family)

Operation: If Condition True

Then 1s → Destination

Else 0s → Destination

Assembler

Syntax: Scc < ea >

Attributes: Size = (Byte)

Description: Tests the speciﬁed condition code; if the condition is true, sets the byte

speciﬁed by the effective address to TRUE (all ones). Otherwise, sets that byte to

FALSE (all zeros). Condition code cc speciﬁes one of the following conditional tests

(refer to Table 3-19 for more information on these conditional tests):

Condition Codes:

Not affected.

Mnemonic Condition Mnemonic Condition

CC(HI) Carry Clear LS Low or Same

CS(LO) Carry Set LT Less Than

EQ Equal MI Minus

F False NE Not Equal

GE Greater or Equal PL Plus

GT Greater Than T True

HI High VC Overflow Clear

LE Less or Equal VS Overflow Set

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-173

Scc Set According to Condition Scc

(M68000 Family)

Instruction Format:

Instruction Fields:

Condition ﬁeld—The binary code for one of the conditions listed in the table.

Effective Address ﬁeld—Speciﬁes the location in which the TRUE/FALSE byte is to be

stored. Only data alterable addressing modes can be used as listed in the

following tables:

*Can be used with CPU32.

NOTE

A subsequent NEG.B instruction with the same effective

address can be used to change the Scc result from TRUE or

FALSE to the equivalent arithmetic value (TRUE = 1, FALSE =

0). In the MC68000 and MC68008, a memory destination is read

before it is written.

1514131211109876543210

0101 CONDITION 1 1

EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-174 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

SUB Subtract SUB

(M68000 Family)

Operation: Destination – Source → Destination

Assembler SUB < ea > ,Dn

Syntax: SUB Dn, < ea >

Attributes: Size = (Byte, Word, Long)

Description: Subtracts the source operand from the destination operand and stores the

result in the destination. The size of the operation is speciﬁed as byte, word, or long.

The mode of the instruction indicates which operand is the source, which is the

destination, and which is the operand size.

Condition Codes:

X — Set to the value of the carry bit.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if an overﬂow is generated; cleared otherwise.

C — Set if a borrow is generated; cleared otherwise.

Instruction Format:

XNZVC

∗∗∗∗∗

1514131211109876543210

1001 REGISTER OPMODE

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-175

SUB Subtract SUB

(M68000 Family)

Instruction Fields:

Opmode ﬁeld

Effective Address ﬁeld—Determines the addressing mode. If the location speciﬁed is a

source operand, all addressing modes can be used as listed in the following

tables:

*For byte-sized operation, address register direct is not allowed.

**Can be used with CPU32.

Byte Word Long Operation

000 001 010 Dn – < ea > → Dn

100 101 110 < ea > – Dn → < ea >

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An* 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)** 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-176 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

SUB Subtract SUB

(M68000 Family)

If the location speciﬁed is a destination operand, only memory alterable addressing

modes can be used as listed in the following tables:

*Can be used with CPU32.

NOTE

If the destination is a data register, it must be speciﬁed as a

destination Dn address, not as a destination < ea > address.

Most assemblers use SUBA when the destination is an address

Addressing Mode Mode Register Addressing Mode Mode Register

Dn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-177

SUBA Subtract Address SUBA

(M68000 Family)

Operation: Destination – Source → Destination

Assembler

Syntax: SUBA < ea > ,An

Attributes: Size = (Word, Long)

Description: Subtracts the source operand from the destination address register and stores

the result in the address register. The size of the operation is speciﬁed as word or long.

Word-sized source operands are sign-extended to 32-bit quantities prior to the

subtraction.

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

Opmode ﬁeld—Speciﬁes the size of the operation.

011—Word operation. The source operand is sign-extended to a long operand and

the operation is performed on the address register using all 32 bits.

111— Long operation.

1514131211109876543210

1001 REGISTER OPMODE

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

4-178 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

SUBA Subtract Address SUBA

(M68000 Family)

Effective Address ﬁeld—Speciﬁes the source operand. All addressing modes can be

used as listed in the following tables:

*Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-179

SUBI Subtract Immediate SUBI

(M68000 Family)

Operation: Destination – Immediate Data → Destination

Assembler

Syntax: SUBI # < data > , < ea >

Attributes: Size = (Byte, Word, Long)

Description: Subtracts the immediate data from the destination operand and stores the

result in the destination location. The size of the operation is speciﬁed as byte, word,

or long. The size of the immediate data matches the operation size.

Condition Codes:

X — Set to the value of the carry bit.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if an overﬂow occurs; cleared otherwise.

C — Set if a borrow occurs; cleared otherwise.

Instruction Format:

XNZVC

∗∗∗∗∗

1514131211109876543210

00000100 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

16-BIT WORD DATA 8-BIT BYTE DATA

32-BIT LONG DATA

Integer Instructions

4-180 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

SUBI Subtract Immediate SUBI

(M68000 Family)

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

Effective Address ﬁeld—Speciﬁes the destination operand. Only data alterable

addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

Immediate ﬁeld—Data immediately following the instruction.

If size = 00, the data is the low-order byte of the immediate word.

If size = 01, the data is the entire immediate word.

If size = 10, the data is the next two immediate words.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-181

SUBQ Subtract Quick SUBQ

(M68000 Family)

Operation: Destination – Immediate Data → Destination

Assembler

Syntax: SUBQ # < data > , < ea >

Attributes: Size = (Byte, Word, Long)

Description: Subtracts the immediate data (1 – 8) from the destination operand. The size

of the operation is speciﬁed as byte, word, or long. Only word and long operations can

be used with address registers, and the condition codes are not affected. When

subtracting from address registers, the entire destination address register is used,

despite the operation size.

Condition Codes:

X — Set to the value of the carry bit.

N — Set if the result is negative; cleared otherwise.

Z — Set if the result is zero; cleared otherwise.

V — Set if an overﬂow occurs; cleared otherwise.

C — Set if a borrow occurs; cleared otherwise.

Instruction Format:

XNZVC

∗∗∗∗∗

1514131211109876543210

0101 DATA 1 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

4-182 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

SUBQ Subtract Quick SUBQ

(M68000 Family)

Instruction Fields:

Data ﬁeld—Three bits of immediate data; 1 – 7 represent immediate values of 1 – 7,

and zero represents eight.

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

Effective Address ﬁeld—Speciﬁes the destination location. Only alterable addressing

modes can be used as listed in the following tables:

*Word and long only.

**Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An* 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)** — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-183

SUBX Subtract with Extend SUBX

(M68000 Family)

Operation: Destination – Source – X → Destination

Assembler SUBX Dx,Dy

Syntax: SUBX – (Ax), – (Ay)

Attributes: Size = (Byte, Word, Long)

Description: Subtracts the source operand and the extend bit from the destination operand

and stores the result in the destination

location. The instruction has two modes:

1. Data register to data register—the data registers specified in the instruction con-

tain the operands.

2. Memory to memory—the address registers specified in the instruction access

the operands from memory using the predecrement addressing mode.

The size of the operand is specified as byte, word, or long.

Condition Codes:

X — Set to the value of the carry bit.

N — Set if the result is negative; cleared otherwise.

Z — Cleared if the result is nonzero; unchanged otherwise.

V — Set if an overﬂow occurs; cleared otherwise.

C — Set if a borrow occurs; cleared otherwise.

NOTE

Normally the Z condition code bit is set via programming before

the start of an operation. This allows successful tests for zero

results upon completion of multiple-precision operations.

XNZVC

∗∗∗∗∗

Integer Instructions

4-184 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

SUBX Subtract with Extend SUBX

(M68000 Family)

Instruction Format:

Instruction Fields:

If R/M = 0, speciﬁes a data register.

If R/M = 1, speciﬁes an address register for the predecrement addressing mode.

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

R/M ﬁeld—Speciﬁes the operand addressing mode.

0 — The operation is data register to data register.

1 — The operation is memory to memory.

If R/M = 0, speciﬁes a data register.

If R/M = 1, speciﬁes an address register for the predecrement addressing mode.

1514131211109876543210

1001REGISTER Dy/Ay 1 SIZE 0 0 R/M REGISTER Dx/Ax

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-185

SWAP Swap Register Halves SWAP

(M68000 Family)

Operation: Register 31 – 16 ←→ Register 15 – 0

Assembler

Syntax: SWAP Dn

Attributes: Size = (Word)

Description: Exchange the 16-bit words (halves) of a data register.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the 32-bit result is set; cleared otherwise.

Z — Set if the 32-bit result is zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

Instruction Field:

XNZVC

—∗∗00

1514131211109876543210

0100100001000 REGISTER

Integer Instructions

4-186 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

TAS Test and Set an Operand TAS

(M68000 Family)

Operation: Destination Tested → Condition Codes; 1 → Bit 7 of Destination

Assembler

Syntax: TAS < ea >

Attributes: Size = (Byte)

Description: Tests and sets the byte operand addressed by the effective address ﬁeld. The

instruction tests the current value of the operand and sets the N and Z condition bits

appropriately. TAS also sets the high-order bit of the operand. The operation uses a

locked or read-modify-write transfer sequence. This instruction supports use of a ﬂag

or semaphore to coordinate several processors.

Condition Codes:

X — Not affected.

N — Set if the most signiﬁcant bit of the operand is currently set; cleared otherwise.

Z — Set if the operand was zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—∗∗00

1514131211109876543210

0100101011

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-187

TAS Test and Set an Operand TAS

(M68000 Family)

Instruction Fields:

Effective Address ﬁeld—Speciﬁes the location of the tested operand. Only data

alterable addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC) — —

,An,Xn) 110 reg. number:An (d

,PC,Xn) — —

MC68020, MC68030, and MC68040 only

(bd,An,Xn)* 110 reg. number:An (bd,PC,Xn)* — —

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) — —

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) — —

Integer Instructions

4-188 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

TRAP Trap TRAP

(M68000 Family)

Operation: 1 → S-Bit of SR

*SSP – 2 → SSP; Format/Offset → (SSP);

SSP – 4 → SSP; PC → (SSP); SSP – 2 → SSP;

SR → (SSP); Vector Address → PC

*The MC68000 and MC68008 do not write vector offset or

format code to the system stack.

Assembler

Syntax: TRAP # < vector >

Attributes: Unsized

Description: Causes a TRAP # < vector > exception. The instruction adds the immediate

operand (vector) of the instruction to 32 to obtain the vector number. The range of

vector values is 0 – 15, which provides 16 vectors.

Condition Codes:

Not affected.

Instruction Format:

Instruction Fields:

Vector ﬁeld—Speciﬁes the trap vector to be taken.

1514131211109876543210

010011100100 VECTOR

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-189

TRAPcc Trap on Condition TRAPcc

(MC68020, MC68030, MC68040, CPU32)

Operation: If cc

Then TRAP

Assembler TRAPcc

Syntax: TRAPcc.W # < data >

TRAPcc.L # < data >

Attributes: Unsized or Size = (Word, Long)

Description: If the speciﬁed condition is true, causes a TRAPcc exception with a vector

number 7. The processor pushes the address of the next instruction word (currently in

the program counter) onto the stack. If the condition is not true, the processor performs

no operation, and execution continues with the next instruction. The immediate data

operand should be placed in the next word(s) following the operation word and is

available to the trap handler. Condition code cc speciﬁes one of the following

conditional tests (refer to Table 3-19 for more information on these conditional tests):

Condition Codes:

Not affected.

Mnemonic Condition Mnemonic Condition

CC(HI) Carry Clear LS Low or Same

CS(LO) Carry Set LT Less Than

EQ Equal MI Minus

F False NE Not Equal

GE Greater or Equal PL Plus

GT Greater Than T True

HI High VC Overflow Clear

LE Less or Equal VS Overflow Set

Integer Instructions

4-190 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

TRAPcc Trap on Condition TRAPcc

(MC68020, MC68030, MC68040, CPU32)

Instruction Format:

Instruction Fields:

Condition ﬁeld—The binary code for one of the conditions listed in the table.

Opmode ﬁeld—Selects the instruction form.

010—Instruction is followed by word-sized operand.

011—Instruction is followed by long-word-sized operand.

100—Instruction has no operand.

1514131211109876543210

0101 CONDITION 11111 OPMODE

OPTIONAL WORD

OR LONG WORD

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-191

TRAPV Trap on Overflow TRAPV

(M68000 Family)

Operation: If V

Then TRAP

Assembler

Syntax: TRAPV

Attributes: Unsized

Description: If the overﬂow condition is set, causes a TRAPV exception with a vector

number 7. If the overﬂow condition is not set, the processor performs no operation and

execution continues with the next instruction.

Condition Codes:

Not affected.

Instruction Format:

1514131211109876543210

0100111001110110

Integer Instructions

4-192 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

TST Test an Operand TST

(M68000 Family)

Operation: Destination Tested → Condition Codes

Assembler

Syntax: TST < ea >

Attributes: Size = (Byte, Word, Long)

Description: Compares the operand with zero and sets the condition codes according to

the results of the test. The size of the operation is speciﬁed as byte, word, or long.

Condition Codes:

X — Not affected.

N — Set if the operand is negative; cleared otherwise.

Z — Set if the operand is zero; cleared otherwise.

V — Always cleared.

C — Always cleared.

Instruction Format:

XNZVC

—∗∗00

1514131211109876543210

01001010 SIZE

EFFECTIVE ADDRESS

MODE REGISTER

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-193

TST Test an Operand TST

(M68000 Family)

Instruction Fields:

Size ﬁeld—Speciﬁes the size of the operation.

00 — Byte operation

01 — Word operation

10 — Long operation

Effective Address ﬁeld—Speciﬁes the addressing mode for the destination operand as

listed in the following tables:

*MC68020, MC68030, MC68040, and CPU32. Address register direct allowed only for word

and long.

**PC relative addressing modes do not apply to MC68000, MC680008, or MC68010.

***Can be used with CPU32.

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An* 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An #<data>* 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

,An) 101 reg. number:An (d

,PC)** 111 010

,An,Xn) 110 reg. number:An (d

,PC,Xn)** 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)*** 110 reg. number:An (bd,PC,Xn)*** 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

Integer Instructions

4-194 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

UNLK Unlink UNLK

(M68000 Family)

Operation: An → SP; (SP) → An; SP + 4 → SP

Assembler

Syntax: UNLK An

Attributes: Unsized

Description: Loads the stack pointer from the speciﬁed address register, then loads the

address register with the long word pulled from the top of the stack.

Condition Codes:

Not affected.

Instruction Format:

Instruction Field:

1514131211109876543210

0100111001011 REGISTER

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-195

UNPK Unpack BCD UNPK

(MC68020, MC68030, MC68040)

Operation: Source (Packed BCD) + Adjustment → Destination (Unpacked BCD)

Assembler UNPACK – (Ax), – (Ay),# < adjustment >

Syntax: UNPK Dx,Dy,# < adjustment >

Attributes: Unsized

Description: Places the two binary-coded decimal digits in the source operand byte into the

lower four bits of two bytes and places zero bits in the upper four bits of both bytes.

Adds the adjustment value to this unpacked value. Condition codes are not altered.

When both operands are data registers, the instruction unpacks the source register

contents, adds the extension word, and places the result in the destination register.

The high word of the destination register is unaffected.

Source:

Intermediate Expansion:

Add Adjustment Word:

Destination:

1514131211109876543210

uuuuuuuuabcdefgh

1514131211109876543210

0000abcd0000efgh

1514131211109876543210

16-BIT EXTENSION

1514131211109876543210

vvvva’b’c’d’wwwwe’f’g’h’

Integer Instructions

4-196 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

UNPK Unpack BCD UNPK

(MC68020, MC68030, MC68040)

When the specified addressing mode is predecrement, the instruction extracts two

binary-coded decimal digits from a byte at the source address. After unpacking the dig-

its and adding the adjustment word, the instruction writes the two bytes to the destina-

tion address. Source:

Intermediate Expansion:

Add Adjustment Word:

Destination:

Condition Codes:

Not affected.

Instruction Format:

76543210

abcdefgh

1514131211109876543210

0000abcd0000efgh

15 0

16-BIT EXTENSION

76543210

vvvva’b’c’d’

wwwwe’f’g’h’

1514131211109876543210

1000REGISTER Dy/Ay 11000R/MREGISTER Dx/Ax

16-BIT EXTENSION: ADJUSTMENT

Integer Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-197

UNPK Unpack BCD UNPK

(MC68020, MC68030, MC68040)

Instruction Fields:

If R/M = 0, speciﬁes a data register.

If R/M = 1, speciﬁes an address register in the predecrement addressing mode.

R/M ﬁeld—Speciﬁes the operand addressing mode.

0 — The operation is data register to data register.

1 — The operation is memory to memory.

If R/M = 0, speciﬁes a data register.

If R/M = 1, speciﬁes an address register in the predecrement addressing mode.

Adjustment ﬁeld—Immediate data word that is added to the source operand.

Appropriate constants can be used as the adjustment to translate from binary-

coded decimal to the desired code. The constant used for ASCII is $3030; for

EBCDIC, $F0F0.